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* soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLERKyösti Mälkki2019-07-133-14/+8
* cpu/x86: Move smm_lock() prototypeKyösti Mälkki2019-07-135-0/+5
* soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSPNico Huber2019-07-131-0/+3
* src: Add missing include <device/pci_ops.h>Elyes HAOUAS2019-07-121-0/+1
* soc/intel/common: Add Coffee Lake H 6+2 Xeon graphics idNico Huber2019-07-122-0/+2
* soc/intel/common: Add CM246 LPC device idNico Huber2019-07-122-0/+2
* soc/intel/cannonlake: Add GPID and CGPM methods to GPIO ASLTim Wawrzynczak2019-07-111-0/+50
* soc/intel/intelblocks/gpio: Always expose GPIO PM constantsTim Wawrzynczak2019-07-111-3/+3
* soc/intel/cannonlake: Make EC S0ix notification optional in LPITTim Wawrzynczak2019-07-111-8/+17
* soc/intel/common: Check bios_size and window_size after MIN operationJohn Zhao2019-07-112-2/+2
* soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timerSubrata Banik2019-07-119-35/+20
* soc/intel/block/cpu: remove unused USE_COREBOOT_NATIVE_MP_INITArthur Heymans2019-07-101-12/+1
* soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size onlyFrans Hendriks2019-07-101-3/+13
* soc/intel: Drop some HAVE_SMI_HANDLER guardsKyösti Mälkki2019-07-102-2/+2
* soc/intel: Remove invalid smm_relocate stubsKyösti Mälkki2019-07-103-32/+0
* arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki2019-07-097-7/+0
* cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki2019-07-0910-10/+0
* arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki2019-07-093-11/+11
* drivers/intel: Move FSP stage_cache implementation into common blockSubrata Banik2019-07-091-0/+13
* soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.hSubrata Banik2019-07-0915-26/+15
* intel/fsp_baytrail: Move TSC_MONOTONIC_TIMERKyösti Mälkki2019-07-081-0/+1
* soc/intel/icelake: Remove redundant gpio.c from Makefile.incSubrata Banik2019-07-071-1/+0
* soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstageFurquan Shaikh2019-07-072-0/+24
* soc/intel/icelake: Get rid of unused dev paramFurquan Shaikh2019-07-071-5/+5
* soc/intel/icelake: Use SA_DEV_ROOT instead of PCH_DEV_PMCFurquan Shaikh2019-07-072-2/+7
* soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev paramFurquan Shaikh2019-07-072-7/+6
* soc/intel/cannonlake: Use SA_DEV_ROOT instead of PCH_DEV_PMCFurquan Shaikh2019-07-072-2/+7
* soc/intel/icelake: Fix outb orderLijian Zhao2019-07-061-2/+2
* soc/intel/cannonlake: Fix outb orderJeremy Soller2019-07-061-2/+2
* soc/intel/cannonlake: Override PRERAM_CBMEM_CONSOLE_SIZE default valueSubrata Banik2019-07-061-0/+4
* soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE widthSubrata Banik2019-07-061-4/+4
* soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-HJeremy Soller2019-07-052-19/+24
* soc/intel/common: Increase SMM_MODULE_STACK_SIZE to 0x800Kane Chen2019-07-041-0/+4
* soc/intel: Replace uses of dev_find_slot()Kyösti Mälkki2019-07-0432-70/+70
* arch/x86: Adjust size of postcar stackKyösti Mälkki2019-07-048-12/+13
* Revert "soc/intel/skylake/romstage: Increase size of postcar stack"Kyösti Mälkki2019-07-041-1/+1
* soc/intel/skylake: Add Kabylake-R microcode update filesArthur Heymans2019-07-031-2/+4
* src: Use CRx_TYPE type for CRxElyes HAOUAS2019-07-021-0/+1
* soc/intel/cannonlake: Add support to log XHCI wake eventsPaul Fagerburg2019-07-022-2/+17
* soc/intel/icelake: Disable HDA based on devicetreeSubrata Banik2019-07-021-1/+3
* Use 3rdparty/intel-microcodeArthur Heymans2019-07-015-11/+27
* {soc,northbridge}/Kconfig: Remove unused CACHE_MRC_SIZE_KBElyes HAOUAS2019-06-281-4/+0
* soc/intel/cannonlake: fix use of legacy 8254 timerMatt DeVillier2019-06-284-13/+12
* soc/intel/cannonlake/Kconfig: Don't have all variants select SOC_INTEL_CANNON...Arthur Heymans2019-06-262-15/+14
* soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTEPatrick Havelange2019-06-251-1/+1
* cbfstool: Drop update-fit optionPatrick Rudolph2019-06-241-1/+1
* Replace ENV_RAMSTAGE with ENV_PAYLOAD_LOADERSubrata Banik2019-06-243-3/+3
* soc/intel: Provide SPD manufacturer ID and module type to SMBIOSDuncan Laurie2019-06-217-6/+40
* soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASEArthur Heymans2019-06-214-8/+8
* cpu/x86/msr: Move IA32_MISC_ENABLE bits to common placeElyes HAOUAS2019-06-211-4/+0
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