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* soc/intel/xeon_sp: Skip locking down TXT related registersArthur Heymans2021-05-201-0/+6
* soc/intel/broadwell: Use Lynx Point IOBP codeAngel Pons2021-05-209-158/+8
* soc/intel/xeon_sp: Remove superfluous printkArthur Heymans2021-05-201-3/+0
* baytrail: Factor out INT15 handlerAngel Pons2021-05-203-0/+104
* soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.aslMaulik V Vaghela2021-05-181-1/+10
* cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans2021-05-1813-13/+0
* intelblocks/gpio: Add NAVFWE bit to PAD_CFG_DW0 mask definitionMaulik V Vaghela2021-05-181-1/+1
* soc/intel/alderlake: mb/intel/sm: Add tcss codeDeepti Deshatty2021-05-183-17/+34
* soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwardsBora Guvendik2021-05-161-5/+6
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar2021-05-161-8/+8
* soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OCNick Vaccaro2021-05-143-0/+23
* soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela2021-05-144-0/+5
* soc/intel/alderlake: Add known GPIO virtual wire informationDeepti Deshatty2021-05-141-0/+27
* soc/intel/alderlake: Add known CPU Port IDs for GPIO communitiesDeepti Deshatty2021-05-142-0/+11
* soc/intel/alderlake: Add IOM PCR PIDDeepti Deshatty2021-05-141-0/+1
* src: Match array format in function declarations and definitionsPatrick Georgi2021-05-138-8/+8
* docs: correct and rewrite documentation regarding n/c / unused padsMichael Niewöhner2021-05-111-2/+3
* src: Drop "This file is part of the coreboot project" linesAngel Pons2021-05-102-2/+0
* soc/intel/cannonlake: Merge soc_memory_init_params() into its callerFelix Singer2021-05-101-14/+5
* soc/intel/skylake: Set proper defaults in chipset devicetreeFelix Singer2021-05-101-3/+3
* soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetrainingMaulik V Vaghela2021-05-102-0/+12
* soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXITKane Chen2021-05-076-6/+38
* soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmasterKane Chen2021-05-073-0/+24
* src: Retype option API to use unsigned integersAngel Pons2021-05-063-3/+3
* Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"Arthur Heymans2021-05-061-13/+13
* soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak2021-05-066-17/+77
* soc/intel/tigkerlake: Add IOM PCR PIDTim Wawrzynczak2021-05-061-0/+1
* soc/intel/tigerlake: Add known CPU Port IDs for GPIO communitiesTim Wawrzynczak2021-05-062-0/+10
* soc/intel/common: Add CPU Port ID field to GPIO communitiesTim Wawrzynczak2021-05-062-0/+10
* soc/intel/tigerlake: Add known GPIO virtual wire informationTim Wawrzynczak2021-05-061-0/+27
* soc/intel/common: Add virtual wire mapping entries to GPIO communitiesTim Wawrzynczak2021-05-062-0/+43
* soc/intel/alderlake: Add CrashLog implementation for Intel ADLFrancois Toguo2021-05-067-1/+349
* soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIOMaulik V Vaghela2021-05-053-100/+237
* soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 regMaulik V Vaghela2021-05-051-0/+8
* drivers/intel/fsp2_0: Fix the FSP-T positionArthur Heymans2021-05-051-10/+1
* soc/intel/xeon_sp: Remove bogus SMRAM lockingArthur Heymans2021-05-051-8/+0
* soc/intel/alderlake: remove duplicate PL2 overrideSumeet R Pawnikar2021-05-041-2/+0
* soc/intel/*: Update data types for variables holding PCH_DEVFN_* macrosTim Wawrzynczak2021-05-034-4/+4
* device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak2021-05-033-51/+20
* soc/intel/alderlake: Enable HWP CPPC support in CBravindr12021-05-031-0/+1
* soc/intel/alderlake: Fill FSPM UPDs for VT-d configurationMeera Ravindranath2021-05-031-3/+30
* soc/intel/cannonlake/include: Drop unused codeFelix Singer2021-05-021-9/+0
* soc/intel/skylake: Remove useless help textsFelix Singer2021-05-021-6/+0
* soc/intel/cannonlake: Remove useless help textsFelix Singer2021-05-021-8/+0
* soc/intel/skylake: Add Kconfig option for LGA1151v2Timofey Komarov2021-05-011-4/+26
* soc/intel/skylake: Add microcodes for Coffee Lake CPUsTimofey Komarov2021-05-012-0/+10
* soc/intel/common/block/hda: Use azalia device codePatrick Rudolph2021-04-282-39/+6
* soc/intel: Add Z370, H310C and B365 device IDsAngel Pons2021-04-282-0/+6
* soc/intel: Add Kaby Lake PCH-U base device IDAngel Pons2021-04-282-0/+2
* soc/intel/skylake: Shorten report_platform PCH-H namesAngel Pons2021-04-281-19/+19
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