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* soc/intel/common/block/smm/smihandler: Fix compilation under x86_64Patrick Rudolph2020-12-011-2/+2
* soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64Patrick Rudolph2020-12-011-0/+8
* soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 supportPatrick Rudolph2020-12-011-0/+11
* soc/intel/common/block/systemagent: Fix compilation on x86_64Patrick Rudolph2020-12-011-2/+2
* soc/intel/skylake: Fix commentFelix Singer2020-11-301-1/+1
* soc/intel/alderlake: Add initial chipset.cbTim Wawrzynczak2020-11-302-0/+71
* soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devicesTim Wawrzynczak2020-11-301-2/+4
* lp4x: Add new memory parts and generate SPDsNick Vaccaro2020-11-301-0/+1
* soc/intel: Configure P2SB before other PCH controllersFurquan Shaikh2020-11-297-13/+48
* soc/intel/alderlake: Add lp5_ccc_config to the board memory configurationSridhar Siricilla2020-11-292-0/+9
* soc/intel/skl: correct OC pin skip value for disabled usb portsMichael Niewöhner2020-11-281-5/+6
* soc/intel/jasperlake: Enable VT-d and generate DMAR TableMeera Ravindranath2020-11-271-0/+13
* soc/intel/{broadwell,quark}: Drop `PEI_DATA` typedefAngel Pons2020-11-252-4/+0
* soc/intel/xeon_sp: Enable SMI handlerRocky Phagura2020-11-2412-19/+205
* soc/intel/xeon_sp: Select INTEL_COMMON_BLOCK_TCOArthur Heymans2020-11-245-0/+50
* soc/intel/xeon_sp: Hook up the PMC driverArthur Heymans2020-11-241-0/+4
* soc/intel/skylake: Support NHLT 1ch DMICBenjamin Doron2020-11-243-0/+47
* soc/intel/skylake: Use correct NHLT_PDM_DEV definitionBenjamin Doron2020-11-241-2/+2
* soc/intel/cannonlake: Add ICC limits for CFL-S DT 4Angel Pons2020-11-231-0/+6
* soc/intel/denverton_ns: Hook up SMMSTOREAngel Pons2020-11-231-0/+25
* soc/intel/alderlake: Update UART0 GPIO as per latest schematicsSubrata Banik2020-11-231-2/+2
* soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZESubrata Banik2020-11-231-3/+3
* soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and ...Bora Guvendik2020-11-221-1/+1
* soc/intel/tigerlake: Fix overlapping memory address used for early GSPI2 and ...Bora Guvendik2020-11-221-1/+1
* soc/intel/xeon_sp: Work around FSP-T not respecting its own APIArthur Heymans2020-11-221-1/+14
* soc/intel/block/pmclib.c: Properly guard apm_control()Arthur Heymans2020-11-221-1/+1
* soc/intel/common/pmc.c Don't implement a weak function that diesArthur Heymans2020-11-221-16/+0
* soc/intel/block/pmc: Only include the PCI driver when it is not hiddenArthur Heymans2020-11-224-1/+9
* soc/intel/block/pmc: Move pmc_set_acpi_mode() to pmc_lib.cArthur Heymans2020-11-224-11/+11
* soc/intel/denverton_ns: Convert to ASL 2.0 syntaxElyes HAOUAS2020-11-224-66/+66
* soc/intel/braswell/bootblock/bootblock.c: Report the FSP-T outputFrans Hendriks2020-11-221-0/+3
* soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBERArthur Heymans2020-11-201-1/+1
* soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDFArthur Heymans2020-11-206-1/+27
* soc/intel/xeon_sp: Use common P2SB functions to generate HPET IOAPICArthur Heymans2020-11-201-3/+3
* soc/intel/apollolake: use P2SB function to generate DMAR IOAPICArthur Heymans2020-11-201-10/+2
* soc/intel/common/block/p2sb: Add ioapic BDF functionsArthur Heymans2020-11-202-0/+22
* soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMARArthur Heymans2020-11-202-3/+6
* soc/intel/apollolake: use P2SB function to generate DMAR HPETArthur Heymans2020-11-201-2/+2
* soc/intel/common/block/p2sb: Add hpet BDF functionsArthur Heymans2020-11-202-0/+31
* soc/intel/common/p2sb: Add helper function to determine p2sb stateArthur Heymans2020-11-201-4/+14
* soc/intel/xeon_sp: Lock down DMICTLArthur Heymans2020-11-201-0/+3
* soc/intel/xeon_sp/cpx: Lock down P2SB SBIArthur Heymans2020-11-202-0/+7
* soc/intel/xeon_sp/{skx,cpx}: Add txt_get_chipset_dpr callbackArthur Heymans2020-11-203-0/+49
* soc/intel/denverton_ns: Initialize thermal configurationJulien Viard de Galbert2020-11-202-0/+20
* soc/intel/denverton_ns: Enable MC ExceptionJulien Viard de Galbert2020-11-201-0/+7
* src/soc/intel/denverton_ns: Use improvement in coreboot since 4.9Julien Viard de Galbert2020-11-201-3/+23
* soc/intel/common: Use per-soc definition for BAR sizesDuncan Laurie2020-11-201-3/+3
* soc/intel/common/block/cse: Clear post code before resetDuncan Laurie2020-11-201-0/+3
* soc/intel/tigerlake: Enable GPIO IOSTANDBY configurationDuncan Laurie2020-11-201-0/+1
* soc/intel/tigerlake: Expose UPD to enable Precision Time MeasurementDuncan Laurie2020-11-202-0/+4
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