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path: root/src/soc/mediatek/mt8195
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* soc/mediatek: Add an overridable function for WDT clear statusRex-BC Chen2021-11-033-5/+16
* soc/mediatek/mt8195: move timer enum variables to timer_v2.hRex-BC Chen2021-11-031-12/+0
* soc/mediatek/mt8195: add apusys init flowFlora Fu2021-11-035-0/+66
* soc/mediatek/mt8195: add tracker dumpZhenguo Li2021-10-133-5/+11
* src/soc to src/superio: Fix spelling errorsMartin Roth2021-10-051-1/+1
* soc/mediatek: add debug dump for ltiming and clock_divRex-BC Chen2021-10-021-0/+7
* soc/mediatek: Fix I2C failures by adjusting AC timing and bus speedDaolong Zhu2021-10-022-49/+240
* soc/mediatek/mt8195: initialize DFDRex-BC Chen2021-09-293-0/+25
* mb/google/cherry: Fix incorrect timestamps in eventlogChen-Tsung Hsieh2021-09-081-0/+2
* soc/mediatek/mt8195: Update clock square settingChun-Jie Chen2021-08-231-2/+8
* soc/mediatek/mt8195: add HDMI low power settingRex-BC Chen2021-08-234-0/+61
* mb/google/cherry: select mmc storage configWenbin Mei2021-08-091-0/+1
* soc/mediatek/mt8195: Add devapc basic driversNina Wu2021-08-044-0/+2068
* helpers: Add GENMASK macroYu-Ping Wu2021-08-022-14/+13
* soc/mediatek/mt8195: modify mt6360 interfaceRex-BC Chen2021-07-212-42/+72
* soc/mediatek/mt8195: redefine mt6360_regulator_idRex-BC Chen2021-07-212-58/+57
* soc/mediatek/mt8195: Get DRAM size from DRAM calibration resultRyan Chuang2021-07-141-1/+18
* soc/mediatek/mt8195: fine tune pmif spi hardware settings for stabilityJames Lo2021-07-122-3/+4
* soc/mediatek/mt8195: Add dramc_param.hRyan Chuang2021-07-071-0/+152
* soc/mediatek/mt8195: Enable DCMGarmin Chang2021-07-072-0/+62
* soc/mediatek/mt8195: Utilize the retry macroYu-Ping Wu2021-06-261-19/+8
* soc/mediatek/mt8195: Support 4 channel DRAM in DPM init flowRyan Chuang2021-06-243-0/+92
* soc/mediatek/mt8195: Add DPM firmware filesRyan Chuang2021-06-232-0/+14
* soc/mediatek/mt8195: Add mt6360 driver for PMIC accessAndrew SH Cheng2021-06-233-83/+202
* soc/mediatek/mt8195: add mt6691 driverhenryc.chen2021-06-183-0/+112
* soc/mediatek/mt8195: add eDP supportJitao Shi2021-06-188-0/+7450
* soc/mediatek/mt8195: Add ddp driver to support eDP outputjason-jh.lin2021-06-163-0/+553
* soc/mediatek/mt8195: Add base addresses for displayJitao Shi2021-06-101-0/+4
* soc/mediatek/mt8195: add power and power control for eDPJitao Shi2021-06-103-0/+25
* soc/mediatek/mt8195: fix GPIO register offsetsZhiqiang Ma2021-06-051-43/+43
* soc/mediatek/mt8195: Enable mt8195 auxadcZhiqiang Ma2021-06-054-1/+44
* soc/mediatek/mt8195: add SPM loaderDawei Chien2021-06-044-14/+1155
* soc/mediatek: Initialize SSPMRex-BC Chen2021-06-033-1/+11
* soc/mediatek/mt8195: Initialize MCUPMalex.miao2021-05-264-0/+22
* soc/mediatek/mt8195: Change fsrc source to ulposcchun-jie.chen2021-05-261-1/+1
* soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWAREYidi Lin2021-05-182-0/+3
* soc/mediatek/mt8195: Initialize DRAM in romstageRex-BC Chen2021-05-144-10/+66
* soc/mediatek/mt8195: change vpp_sel default mux for 4k supportNancy.Lin2021-05-131-2/+2
* soc/mediatek/mt8195: configure DMA buffer in DRAMRex-BC Chen2021-05-132-0/+8
* soc/mediatek/mt8195: Enable SCP SRAMRex-BC Chen2021-05-133-0/+34
* soc/mediatek/mt8195: Enable and initialize eintYidi Lin2021-05-112-0/+3
* soc/mediatek/mt8195: Disable UFS reference clockYidi Lin2021-05-113-1/+4
* soc/mediatek/mt8195: Add RTC driverYuchen Huang2021-05-105-0/+257
* soc/mediatek/mt8195: Add clk_buf driverYuchen Huang2021-05-101-0/+1
* soc/mediatek/mt8195: Configure eMMC and SDCardWenbin Mei2021-05-101-0/+1
* soc/mediatek/mt8195: Add i2c driver supportkewei xu2021-05-103-0/+230
* soc/mediatek/mt8195: Add mt6360 driver for LDO accessAndrew SH Cheng2021-05-102-0/+357
* soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cacheYidi Lin2021-05-073-0/+34
* soc/mediatek/mt8195: Add mtcmos init supportWeiyi Lu2021-05-053-0/+128
* soc/mediatek/mt8195: Add NOR-Flash supportRex-BC Chen2021-05-054-0/+24
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