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* mediatek/mt8192: memlayout: Add DRAM DMA regionYidi Lin2020-11-204-3/+26
* soc/mediatek/mt8192: Enable MT8192 auxadc driverPo Xu2020-11-204-0/+46
* soc/mediatek: Move auxadc driver from MT8183 to commonPo Xu2020-11-204-13/+22
* mb/google/asurada: Implement enable_regulator and regulator_is_enabledYidi Lin2020-11-181-0/+5
* mb/google/asurada: Implement board-specific regulator controlsYidi Lin2020-11-182-0/+17
* soc/mediatek/mt8192: add pmic MT6315 driverHsin-Hsiung Wang2020-11-184-0/+346
* soc/mediatek/mt8192: add pmic MT6359P driverHsin-Hsiung Wang2020-11-184-0/+502
* soc/mediatek/mt8192: add pmif driverHsin-Hsiung Wang2020-11-1813-2/+1440
* soc/mediatek/mt8192: Reserve 44K SRAM for MCUPM working bufferYidi Lin2020-11-161-5/+10
* soc/mediatek/mt8192: Do dram full calibrationHuayang Duan2020-10-292-8/+84
* soc/mediatek/mt8192: update descriptions for dram configXi Chen2020-10-261-2/+8
* soc/mediatek/mt8192: add dram log prefixXi Chen2020-10-231-6/+6
* soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cacheCK Hu2020-10-233-0/+33
* soc/mediatek/mt8192: enable CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWAREIkjoon Jang2020-10-222-0/+3
* soc/mediatek/mt8192: Add board-specific regulator APIsYidi Lin2020-10-221-0/+19
* soc/mediatek/mt8192: Do dram fast calibrationHuayang Duan2020-10-206-2/+155
* soc/mediatek/mt8192: Refactor USB code among similar SoCsZhanyong Wang2020-10-123-0/+40
* soc/mediatek: Add function to measure clock frequency of MT8192Weiyi Lu2020-10-093-0/+75
* soc/mediatek: Add function to raise the CPU frequency of MT8192Weiyi Lu2020-10-085-3/+29
* soc/mediatek/mt8183: Enable CA perbit mechanismHuayang Duan2020-09-258-54/+449
* soc/mediatek/mt8192: Init PLL in bootblockCK Hu2020-09-172-0/+3
* soc/mediatek/mt8192: Add mtcmos init supportWeiyi Lu2020-09-174-0/+285
* soc/mediatek: move power status bits under each chipWeiyi Lu2020-09-163-5/+4
* include/console/uart: make index parameter unsignedFelix Held2020-09-121-4/+4
* soc/mediatek: Drop unneeded empty linesElyes HAOUAS2020-09-109-10/+0
* soc/mediatek/mt8192: Add SPI flash controller dual read functionCK Hu2020-09-082-1/+7
* soc/mediatek/mt8192: Add SPI flash controller DMA read functionCK Hu2020-09-081-9/+47
* {include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik2020-09-012-6/+6
* soc/mediatek/mt8192: Use SPI-NOR as flash controllerCK Hu2020-08-284-0/+265
* soc/mediatek: Include addressmap.h in gpio_common.hCK Hu2020-08-261-0/+1
* soc/mediatek/mt8192: Add dramc param structHuayang Duan2020-08-253-0/+294
* src: Remove unused 'include <delay.h>'Elyes HAOUAS2020-08-182-2/+0
* soc/mediatek/mt8192: Initialize watch dog in bootblockCK Hu2020-08-172-0/+3
* soc/mediatek/mt8192: Initialize mmu in bootblockCK Hu2020-08-172-0/+11
* soc/mediatek/mt8192: Add spi driverQii Wang2020-08-133-0/+191
* soc/mediatek/mt8192: Add DRAM resource in ramstageCK Hu2020-08-132-0/+31
* soc/mediatek/mt8192: Initialize build rulesCK Hu2020-08-131-0/+31
* soc/mediatek/mt8192: Add a placeholder for the EMI driverCK Hu2020-08-132-0/+20
* soc/mediatek/mt8192: Add PLL and clock init supportWeiyi Lu2020-08-126-3/+2201
* soc/mediatek/mt8192: Add gpio driverCK Hu2020-08-123-0/+848
* soc/mediatek/mt8183: Transfer ddr geometry type to dram blobHuayang Duan2020-08-121-3/+8
* soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192CK Hu2020-08-083-0/+103
* soc/mediatek/mt8183: Set MMU default map length to 8GB befor mem initHuayang Duan2020-08-061-2/+2
* soc/mediatek/mt8183: Add ddr geometry to support 6GB, 8GB DDR bootupHuayang Duan2020-08-064-5/+14
* soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density valueHuayang Duan2020-08-063-20/+157
* soc/mediatek/mt8183: Add missing register settings for channelsHuayang Duan2020-08-063-35/+59
* Change all assert(0) to BUG()Julius Werner2020-08-031-1/+1
* src/soc/mediatek: Add include <types.h>Elyes HAOUAS2020-07-266-0/+6
* src: Remove unused 'include <stdint.h>Elyes HAOUAS2020-07-141-1/+0
* treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh2020-06-134-0/+8
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