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* coreboot_tables: Drop uart PCI addrArthur Heymans2022-10-261-1/+0
* soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MITRex-BC Chen2022-10-251-1/+1
* soc/mediatek/mt8188: Update mtcmos settings for display and audioBo-Chen Chen2022-10-255-21/+34
* soc/mediatek/mt8188: Add eDP support for firmware displayBo-Chen Chen2022-10-253-0/+17
* soc/mediatek/mt8188: Add ddp driver to support eDP outputNathan Lu2022-10-254-0/+461
* soc/mediatek/mt8188: Rename SPM registerBo-Chen Chen2022-10-253-4/+4
* soc/mediatek: Add support for input 1P mode of dp_intfRex-BC Chen2022-10-254-32/+48
* soc/mediatek: Move DP drivers to commonBo-Chen Chen2022-10-258-13/+14
* soc/mediatek: Unify PLL function namesRex-BC Chen2022-10-219-16/+19
* soc/mediatek/mt8186: Add support for PMIC MT6315Sen Chu2022-10-2110-3/+374
* soc/mediatek: Move SPMI interface configuration to SoC folderSen Chu2022-10-215-20/+74
* soc/mediatek/mt8186: Add PMIF_SPMI_IOCFG_DEFAULT_SETTING Kconfig optionRex-BC Chen2022-10-213-1/+10
* soc/mediatek/mt8186: Add PWRAP_WITH_PMIF_SPMI Kconfig optionRex-BC Chen2022-10-213-1/+9
* soc/mediatek/mt8186: Add support for reading CPU IDRex-BC Chen2022-10-214-0/+30
* soc/mediatek/mt8186: Add DEVAPC settings for ADSPTinghan Shen2022-10-144-3/+151
* soc/mediatek/mt8186: Inititalize ADSPTinghan Shen2022-10-145-0/+39
* soc/mediatek/mt8186: Add mtcmos power-on control for ADSPMandy Liu2022-10-144-1/+44
* soc/mediatek/mt8186: Enable ADSP clockMandy Liu2022-10-141-2/+5
* soc/mediatek/mt8186: Allow SCP to access H264 encoderRunyang Chen2022-09-261-1/+1
* soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registersLiju-Clr Chen2022-09-222-0/+10
* soc/mediatek: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-145-7/+7
* soc/mediatek/mt8188: Set PLLs to hardware default valuesGarmin Chang2022-09-141-84/+84
* soc/mediatek/mt8188: Fix indention in pll.cGarmin.Chang2022-09-141-1/+1
* soc/mediatek/mt8188: Change vpp_sel default mux for 4k supportGarmin Chang2022-09-141-2/+2
* soc/mediatek/mt8188: Fix some wrong settings for PLLsGarmin Chang2022-09-141-18/+18
* timer: Change timer util functions to 64-bitRob Barnes2022-09-145-9/+9
* soc/mediatek/mt8186: Enable lastbus debug hardwareot_zhenguo.li2022-09-094-0/+89
* soc/mediatek/mt8186: Enable the protection of DEVAPCRunyang Chen2022-09-091-0/+1
* soc/mediatek/mt8186: Complete DEVAPC settingsRunyang Chen2022-09-092-375/+399
* soc/mediatek/mt8186: Enable CPU power hardware tracking for PMIC MT6366Sen Chu2022-09-091-0/+9
* src: De-conflict CALIBRATION_REGION definitionsMartin Roth2022-09-081-4/+4
* soc/mediatek/mt8188: Enable ARM Trusted Firmware integrationRex-BC Chen2022-09-082-0/+3
* mb/google/geralt: Pass reset gpio parameter to BL31Bo-Chen Chen2022-09-071-0/+1
* soc/mediatek: a common implementation to register BL31 resetHung-Te Lin2022-09-076-0/+37
* soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxesJohnson Wang2022-09-071-4/+3
* soc/mediatek/mt8188: Add SPM loader and initialize SPM in RAM stageRex-BC Chen2022-08-315-17/+628
* soc/mediatek: Move some SPM functions to commonBo-Chen Chen2022-08-318-552/+232
* soc/mediatek/mt8188: Use MHz as unit for current_clkBo-Chen Chen2022-08-313-3/+9
* soc/mediatek/mt8188: Add DEVAPC basic driverNina Wu2022-08-315-0/+1683
* soc/mediatek: Move common DEVPAC enums and functions to commonBo-Chen Chen2022-08-318-118/+74
* soc/mediatek/mt8188: Initialize DPM in ramstageXi Chen2022-08-311-0/+5
* soc/mediatek/mt8188: Support 4 channel DRAM in DPM init flowXi Chen2022-08-312-0/+3
* soc/mediatek/mt8188: Add DPM firmware filesXi Chen2022-08-312-0/+14
* soc/mediatek: Move dpm_4ch.c to commonXi Chen2022-08-312-1/+1
* soc/mediatek/mt8188: Enable USE_CBMEM_DRAM_INFOXi Chen2022-08-273-20/+3
* soc/mediatek: Move emi.c to common folderRex-BC Chen2022-08-272-7/+2
* soc/mediatek/mt8188: Add DRAM fast calibration supportXi Chen2022-08-272-1/+65
* soc/mediatek/mt8188: Add DRAM full calibration supportXi Chen2022-08-276-15/+114
* soc/mediatek/mt8186: spm: Remove redundant callYidi Lin2022-08-181-1/+0
* soc/mediatek/mt8188: Initialize DFDRex-BC Chen2022-08-132-0/+12
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