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* soc/mediatek/mt8192: devapc: update domain remap settingNina Wu2021-05-052-15/+54
* soc/mediatek/mt8195: Add mtcmos init supportWeiyi Lu2021-05-055-0/+137
* soc/mediatek: Move the power domain data under each SoCWeiyi Lu2021-05-055-22/+71
* soc/mediatek/mt8195: Add NOR-Flash supportRex-BC Chen2021-05-054-0/+24
* soc/mediatek/mt8195: Add SPI driver supportQii Wang2021-05-054-5/+114
* soc/mediatek: Move the common part of SPI drivers to common/Rex-BC Chen2021-05-058-155/+68
* soc/mediatek/mt8195: add pmif/spmi/pmic driverRex-BC Chen2021-05-0515-44/+946
* soc/mediatek/mt8192: devapc: Add ADSP domain settingTinghan Shen2021-04-302-2/+4
* soc/mediatek/mt8195: Add PLL and clock init supportWeiyi Lu2021-04-286-0/+1876
* soc/mediatek: Move the common part of PMIC drivers to common/Yidi Lin2021-04-2821-1053/+1100
* soc/mediatek/mt8195: Add GPIO driverPo Xu2021-04-264-0/+613
* soc/mediatek/mt8195: Add timer supportYidi Lin2021-04-2612-48/+158
* soc/mediatek/mt8192: Remove redundant SPM register definitionYidi Lin2021-04-263-10/+4
* soc/mediatek/mt8195: add register definitionsYidi Lin2021-04-263-0/+1445
* soc/mediatek/mt8195: Initialize watchdogYidi Lin2021-04-266-1/+18
* soc/mediatek: Move mt8192 ufs driver to commonYidi Lin2021-04-213-4/+4
* src/mediatek: Move mt8192 eint driver to commonYidi Lin2021-04-213-3/+3
* soc/mediatek: Remove misleading memory logsYu-Ping Wu2021-04-161-15/+7
* soc/mediatek: Include sdram_info in ddr_base_infoYu-Ping Wu2021-04-143-28/+27
* soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoCYidi Lin2021-04-1311-0/+302
* mb/google/asurada: select mmc storage configWenbin Mei2021-04-091-0/+1
* soc/mediatek: add new driver 'msdc' for eMMCWenbin Mei2021-04-092-0/+657
* soc/mediatek: dsi: fine tune the delta time for EoTpJitao Shi2021-04-081-1/+1
* soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_ENDJitao Shi2021-03-272-1/+10
* soc/mediatek: Use MRC cache API for asuradaYu-Ping Wu2021-03-245-68/+54
* soc/mediatek/mt8192: Enlarge ROMSTAGE to 272KYu-Ping Wu2021-03-241-3/+3
* soc/mediatek/mt8192: devapc: Add SCP domain settingTinghan Shen2021-03-223-0/+15
* vendorcode/mt8192: devapc: fix register offset for PCIe domainNina Wu2021-03-171-1/+1
* cbfs: Remove prog_locate() for stages and rmodulesJulius Werner2021-03-162-8/+0
* soc/mediatek/mt8192: adjust i2c "tLOW" and "tSU,STO"Daolong Zhu2021-03-161-3/+29
* soc/mediatek/mt8192: devapc: Add domain remap settingNina Wu2021-03-152-14/+76
* mb/google/asurada: revise PMIC and RTC initializationYidi Lin2021-03-156-29/+2
* soc/mediatek/mt8192: mt6315: revise initial settingHsin-Hsiung Wang2021-03-101-5/+4
* soc/mediatek/mt8192: mt6315: update initial flowHsin-Hsiung Wang2021-03-102-20/+20
* soc/mediatek/mt8192: mt6315: update correct slave idHsin-Hsiung Wang2021-03-101-1/+1
* soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 400KYu-Ping Wu2021-03-081-1/+1
* soc/mediatek/mt8173,mt8183: revise SOC DRAM implementationXi Chen2021-03-089-103/+86
* soc/mediatek/mt8192: initialize DRAM using vendor reference codeHuayang Duan2021-03-0813-12631/+4
* soc/mediatek/common: Move DRAM implementation from mt8192 to commonXi Chen2021-03-0816-67/+244
* mb/google/asurada: Enable RTC for event logYu-Ping Wu2021-02-251-0/+2
* memlayout: Store region sizes as separate symbolsJulius Werner2021-02-193-6/+6
* soc/mediatek: Remove unused <string.h>Elyes HAOUAS2021-02-164-4/+0
* soc/mediatek: Remove unused <console/console.h>Elyes HAOUAS2021-02-153-3/+0
* soc/mediatek/mt8192: Use LZ4 compression for MCUsYu-Ping Wu2021-02-051-1/+1
* soc/mediatek/mt8192/spm.c: Add missing <string.h>Elyes HAOUAS2021-02-041-1/+1
* src: Remove unused <boardid.h>Elyes HAOUAS2021-02-031-1/+0
* soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE sizeYu-Ping Wu2021-02-011-5/+10
* mb/google/asurada: Improve boot time by raising little CPU frequencyYidi Lin2021-01-281-0/+2
* soc/mediatek/mt8192: Implement dram all channel calibrationHuayang Duan2021-01-282-0/+357
* soc/mediatek/mt8192: Add mt6315_romstage_initYidi Lin2021-01-282-0/+6
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