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* soc/mediatek: Move common definitions to dramc_soc_common.hRex-BC Chen2022-08-034-48/+28
| | | | | | | | | | | | | | Some definitions are the same in dramc_soc.h for MT8192, MT8195 and MT8186, so we move them to dramc_soc_common.h TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add SPI supportLiya Li2022-07-293-1/+102
| | | | | | | | | | | | | | | | The gpios and the tick delay register are different between MT8188 and previous MediaTek SoCs, so we need to add this patch to support SPI. TEST=build pass BUG=b:236331724 Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com> Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay settingRex-BC Chen2022-07-296-8/+13
| | | | | | | | | | | | | | | MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which is different from previous SoCs, so we define a macro to get the designated register. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add clk_buf support in romstageSong Fan2022-07-291-0/+1
| | | | | | | | | | | | TEST=build pass. BUG=b:233720142 Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com> Change-Id: Ic300b70a38ac204b098ca9ab15cf7045b66fd76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66182 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add RTC supportSong Fan2022-07-292-0/+94
| | | | | | | | | | | | | | Add RTC header file for SoC-specific settings. Add RTC support in romstage. TEST=build pass. BUG=b:233720142 Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com> Change-Id: I38115ce0c9a4e1c1b2b7c8e6d40f47e99f7f86b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66181 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move common definitions from rtc.h to rtc_reg_common.hRex-BC Chen2022-07-295-528/+163
| | | | | | | | | | | | | | | Move the common definitions to rtc_reg_common.h, so we can reuse those definitions on MT8188. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add AUXADC supportHui Liu2022-07-293-0/+35
| | | | | | | | | | | TEST=get voltage as 340mV for channel 0 in MTK EVB. BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: Idd1edcce6cb62fcf6991bb9342c409150989c5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/66121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move struct mtk_auxadc_regs to auxadc_common.hRex-BC Chen2022-07-295-44/+11
| | | | | | | | | | | | | | The AUXADC register definitions are the same for all MediaTek SoCs, so we move struct mtk_auxadc_regs to auxadc_common.h. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Skip PCIe ops for eMMC SKUsYu-Ping Wu2022-07-271-2/+7
| | | | | | | | | | | | | | | | | To avoid unnecessary PCIe early initialization for non-NVMe devices (which would take about 150ms on dojo), skip setting PCIe ops when initializing mt8195 SoC. BUG=b:238850212 TEST=emerge-cherry coreboot TEST=Dojo SKU1 (eMMC) boot time <= 1s BRANCH=cherry Change-Id: I8945890ba422c0c4eb42683935220b7afbb80dfd Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/cherry: Introduce mainboard_needs_pcie_initYu-Ping Wu2022-07-271-0/+3
| | | | | | | | | | | | | | | | | | Implement mainboard_needs_pcie_init() for cherry as a callback for mt8195 SoC to determine whether to initialize PCIe. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:238850212 TEST=emerge-cherry coreboot BRANCH=cherry Change-Id: I2ed0ceeb37d2924ca16485fb2d130959a7eff102 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* soc/mediatek/mt8188: Initialize SSPMRex-BC Chen2022-07-264-1/+13
| | | | | | | | | | | | | | | | | | | | | SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. It takes 21 ms to load sspm.bin. coreboot logs: CBFS: Found 'sspm.bin' @0x21680 size 0xa815 in mcache @0xffffeac4 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137348 bytes) TEST=we can see the sspm logs. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ib6443b64734048c1d71eeac650f36d7c4ac709cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Initialize MCUPMRex-BC Chen2022-07-264-0/+24
| | | | | | | | | | | | | | | | | | | Load MCUPM firmware and boot up MCUPM in ramstage. It takes 41 ms to load mcupm.bin. coreboot logs: CBFS: Found 'mcupm.bin' @0x12580 size 0xf0c6 in mcache @0xffffead0 mtk_init_mcu: Loaded (and reset) mcupm.bin in 41 msecs (122184 bytes) TEST=we can see the mcupm logs after reset releases. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Id1e62d9d6ede1c453e03eeda0d9b16fafa9e2372 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Add eMMC and SD card configurationsAndy-ld Lu2022-07-222-0/+116
| | | | | | | | | | | | | | | | | | | | Geralt reference design has both eMMC and SD card interfaces, so we have to configure both in ramstage. Implement msdc.c (mass storage device class) to place the eMMC and SD card drivers. This implementation is based on chapter 5.9 in MT8188 Functional Specification. TEST=boot to kernel using emmc successfully. BUG=b:236331724 Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com> Change-Id: I6594c8466a133d3fdb0084716acca8dcf785f94f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65975 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Implement regulator interfaceHui Liu2022-07-221-0/+2
| | | | | | | | | | | | | Control regulator more easily with regulator interface. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I9727475774b3b9a8dcd49e5e60e133f9d745b407 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65875 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google: Use boolean type for "enable" argument for regulatorRex-BC Chen2022-07-213-7/+6
| | | | | | | | | | | | | | | Because 0 and 1 are the only possible values, 1. Change input argument "enable" of mainboard_enable_regulator to bool. 2. Change return value of mainboard_regulator_is_enabled() to bool. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google: Replace some strings in regulator.cRex-BC Chen2022-07-212-5/+4
| | | | | | | | | | | | | | | | From comments of CB:65875, we replace *_vol to *_voltage. s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/ s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/ TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Add VMCH, VMC support for MT8188Hui Liu2022-07-213-4/+92
| | | | | | | | | | | | | | For MT8188, we need to enable and adjust VMCH and VMC to support SD cards. Therefore, we add VPA and VSIM1 voltage adjustment APIs. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I03938f9ef17a0bdd615bcbbfc7b59fa5acb8fbfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65874 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add PMIF and PMIC init supportHui Liu2022-07-219-0/+780
| | | | | | | | | | | | | | | | | | Add PMIF, SPI, SPMI and PMIC init code. These PMIC settings are used by MediaTek internally. We can find these registers in "MT6365_PMIC_Data_Sheet_V1.4.pdf" and "MT6315 datasheet v1.3.pdf". The setting values are provided by MeidaTek designers. TEST=build pass BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I05a51894b130a59c28d957b64d6401c8bb9cee91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Create a function to check ulposcRex-BC Chen2022-07-212-8/+19
| | | | | | | | | | | | | | We will use the same drivers for checking ulposc in MT8188, so we add a new function pmif_ulposc_check() to common. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I40136eaeb2c08a97cd65bfb8a81f2f24739d4d51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65841 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move SPMI device table to SoC folderHui Liu2022-07-137-21/+51
| | | | | | | | | | | | | | | | | The SPMI devices on MT8188 are different from previous SoCs, so we move them to SoC folder. We also move SoC-specific definitions to soc/pmif.h. TEST=build pass BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I666c2a8222a2bd8cd460e2225a7ae48b001da9d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65757 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: add usb host supportShaocheng Wang2022-07-134-1/+52
| | | | | | | | | | | | | | Add usb host function support. TEST=read usb data successfully. BUG=b:236331724 Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Change-Id: I3494b687b811466cb6b988164d3c5b6fecc3016a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65754 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Enable mmu operation for L2C SRAM and DMARex-BC Chen2022-07-132-0/+4
| | | | | | | | | | | | | | | | | | | | - Turn off L2C SRAM and reconfigure as L2 cache: Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. - Configure DMA buffer in DRAM: Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I10f1cb8c62dfa78f59a4a5ea6087609668a0c2aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65753 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add video/audio mtcmos settingRex-BC Chen2022-07-131-0/+48
| | | | | | | | | | | | | Add power domain data for video and audio. TEST=build pass BUG=b:233720142 Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: Ic5fd496cbc6904b42eae28a62bf00a71f0ef508d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Add PLL and clock init supportgarmin chang2022-07-138-1/+3478
| | | | | | | | | | | | | | | | | Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. For usb clock setting, we also implement mt_pll_usb_clock_setting() to enable usb clock for all ports. TEST=build pass BUG=b:233720142 Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: I03cb5a4c6fa5ddad7da6f955d0c6d0b3395503e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Add mt_pll_set_usb_clock() to enable usb clockRex-BC Chen2022-07-123-2/+8
| | | | | | | | | | | | | | | There are clock settings for usb in mt8195 and mt8188, so we add a new function which is implemented in pll.c to do this. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I40b358b197541bc5281645879553340059829db3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65750 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Add I2C driver supportkewei.xu2022-07-123-0/+200
| | | | | | | | | | | | | | Add I2C controller drivers. TEST=build pass BUG=b:233720142 Signed-off-by: kewei.xu <kewei.xu@mediatek.corp-partner.google.com> Change-Id: I7d19df3571e5588c7b20d9c7f26fa177b2221851 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Add NOR-Flash supportRex-BC Chen2022-07-075-2/+49
| | | | | | | | | | | | | | Add NOR-Flash drivers for flash read/write. TEST=read nor flash data successfully. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I4e84fc023111b86f7f4984020d24811e3361ba03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65621 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move FLASH_DUAL_READ to commonRex-BC Chen2022-07-065-22/+11
| | | | | | | | | | | | | | | | | | FLASH_DUAL_READ is a common configuration for all MediaTek SoCs, so we move it to common folder and select it in SoCs' Kconfig. As suggested in CB:58837, we also rename FLASH_DUAL_READ to FLASH_DUAL_IO_READ to reduce confusion. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: If267a332519412a7919c5b7817047fabe4a564c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65620 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Add GPIO driversGuodong Liu2022-07-064-0/+669
| | | | | | | | | | | | | | Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:233720142 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I0a2a5178949e9ad3e033ac332e0f1e8565e39b3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65619 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move some gpio functions to common/gpio_op.cRex-BC Chen2022-07-068-180/+69
| | | | | | | | | | | | | | | | gpio_set_pull(), gpio_set_pull_pu_pd() and gpio_set_spec_pull_pupd() can be reused for mt8192, mt8195 and mt8186, so move it to new file "gpio_op.c" in common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I81ab9b01ee20fccf3ef29c5902597b5045d3e36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65641 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add timer supportBo-Chen Chen2022-07-061-1/+1
| | | | | | | | | | | | | | Add timer drivers to Makefile. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I0e3e58c7118a18e738a5abba391db0be9cfd7bf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65588 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Make timer_prepare() a common functionRex-BC Chen2022-07-064-18/+2
| | | | | | | | | | | | | | | timer_prepare() is the same for MT8195 and MT8186, so move it to common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I91a6f4ecc665a058cb7a0ba96c15b27d6dc97d13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65602 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Initialize watchdogBo-Chen Chen2022-07-064-0/+37
| | | | | | | | | | | | | | | | | Add watchdog support for MT8188. This implementation is based on chapter 3.10.10 in MT8188 Functional Specification. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iaf56c78d89af53d0272583b463c050e69bbeb07a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65587 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move wdt_set_req() to common folderBo-Chen Chen2022-07-0612-50/+73
| | | | | | | | | | | | | | | | | | | There are more and more variables which are SoC-specific, so add soc/wdt.h for each SoC and rename common/wdt.h to common/wdt_common.h. wdt_set_req() is almost the same for mt8192, mt8195 and mt8186, so move it to a common file wdt_req.c. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7a334b3e7cd4f24a848dd31aca546dc7236d5fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65636 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Add a stub implementation of the MT8188 SoCRex-BC Chen2022-07-0412-0/+324
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add new folder and basic drivers for Mediatek SoC 'MT8188'. Difference of modules including in this patch between MT8188 and existing SoCs: Timer: Similar to MT8195 and MT8186, MT8188 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. The implementation is based on these files: MT8188G_Application Processor Technical Brief_v0.4.pdf MT8188G_Functional Specification v0.4.pdf MT8188 Application Processor Registers-1.pdf MT8188 Application Processor Registers-2.pdf TEST=saw the coreboot uart log to bootblock BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3320f3d49a9b9ed781ceb812e4341e379db4ac20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65585 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org>
* soc/mediatek: Do resource transitionKyösti Mälkki2022-06-265-5/+5
| | | | | | | | Change-Id: I668a39c603870329fd1528ddc5f3a42a379e1e76 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65267 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/soc: Get rid of most src/soc/Kconfig filesMartin Roth2022-06-241-2/+0
| | | | | | | | | | | | | | | Most of the src/soc/Kconfig files are only there for AMD and Intel to load the main SoC Kconfig files before any common files. That can be done in src/Kconfig instead. Moving the loads to the lower level allows the removal of all but the Intel soc/Kconfig file, which can be removed in a follow-on patch. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* soc/mediatek: Clean up Makefile.inc for mt8186, mt8192 and mt8195Yidi Lin2022-06-243-112/+47
| | | | | | | | | | | | | | | | | | Clean up Makefile.inc by sorting entries and moving common entries to all-y. In this way it is more clear to know what drivers have been involved in each stage and the hardware differences between each SoC. BUG=none TEST=emerge-corsola coreboot TEST=emerge-asurada coreboot TEST=emerge-cherry coreboot Change-Id: Idfc7de36ebf36650f7c6bd1584ef77e2a540cde9 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65315 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-225-5/+5
| | | | | | | | | | | | There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: pass access mode to the payloadWenbin Mei2022-06-121-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Some eMMCs (for example, Kingston-EMMC64G-TX29-HP) may enter the ready state by sending CMD1 twice. If it is in the ready state, then the payload (for example, depthcharge) will not send CMD1, but the access mode is only available from the response of CMD1. Therefore, we need to pass the access mode to the payload by defining the following types: - MMC_STATUS_CMD1_READY: in ready state and access mode is byte mode. - MMC_STATUS_CMD1_READY_HCS: in ready state and access mode is sector mode. BUG=b:234672726 BRANCH=cherry TEST=boot ok Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Iad905781d8ba0105911cf87a6b845cd8df57521e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65054 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* Replace some ENV_ROMSTAGE with ENV_RAMINITKyösti Mälkki2022-06-071-1/+1
| | | | | | | | | | | | | With a combined bootblock+romstage ENV_ROMSTAGE might no longer evaluate true. Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/mediatek: Rename mtk_wdt_preinit() to mtk_wdt_set_req()Rex-BC Chen2022-06-036-5/+7
| | | | | | | | | | | | | | | | | | To simplify the calling sequence for mtk_wdt_preinit() and we always adjust request setting in mtk_wdt_preinit(), we rename mtk_wdt_preinit() to mtk_wdt_set_req() and call it in mtk_wdt_init(). From this modification, we can also enable thermal hardware reset feature (CB:64676, CB:64675) in MT8192 and MT8195. BUG=none TEST=build pass Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186/pll.c: Fix typo in log messageElyes Haouas2022-06-011-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ied8eb0fb51d0521eedd8ff77b1083813d3843570 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* soc/mediatek/mt8192: Enable thermal hardware resetRex-BC Chen2022-05-282-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | Under the current watchdog setting, the system will not reboot when the temperature is too high. To enable thermal hardware reset, we need to enable thermal control request and set it to reboot mode. Note that because thermal throttle (by lowering cpu frequency) is currently enabled, the thermal hardware reset shouldn't be triggered under normal circumstances. This feature is only for new hardware structure for thermal. Therefore, we only need to apply it on MT8192/MT8195/MT8186. This setting is based on thermal and watchdog section of MT8192 Function Specification. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I98b062c2070384527624c3bcf0dfded25a2c8ce4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64676 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Enable thermal hardware resetRex-BC Chen2022-05-281-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Under the current watchdog setting, the system will not reboot when the temperature is too high. To enable thermal hardware reset, we need to enable thermal control request and set it to reboot mode. Note that because thermal throttle (by lowering cpu frequency) is currently enabled, the thermal hardware reset shouldn't be triggered under normal circumstances. This feature is only for new hardware structure for thermal. Therefore, we only need to apply it on MT8192/MT8195/MT8186. This setting is based on thermal and watchdog section of MT8195 Function Specification. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia6489bb953d148a43af173454d6f2b3e2a1dfcf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64675 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Enable thermal hardware resetRunyang Chen2022-05-282-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Under the current watchdog setting, the system will not reboot when the temperature is too high. To enable thermal hardware reset, we need to enable thermal control request and set it to reboot mode. Note that because thermal throttle (by lowering cpu frequency) is currently enabled, the thermal hardware reset shouldn't be triggered under normal circumstances. This feature is only for new hardware structure for thermal. Therefore, we only need to apply it on MT8192/MT8195/MT8186. This setting is based on thermal and watchdog section of MT8186 Function Specification. BUG=none TEST=emerge-corsola coreboot TEST=thermal hardware reset is working. Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: Id2ed55e6d4f4eec450bf7c849f726a389eeb6694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64659 Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Configure SCP core 2 domain settingTinghan Shen2022-05-251-1/+3
| | | | | | | | | | | | | | | | | | SCP core 2 is enabled for MT8195 camera feature. It requires the same register access permission as SCP core 1. Therefore, we configure the same domain ID for both cores. BRANCH=cherry BUG=b:193814857 TEST=cherry boot ok Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Change-Id: Idf335593936b12c083c926a252fa99c3b76cda6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64575 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* CBMEM: Change declarations for initialization hooksKyösti Mälkki2022-05-201-1/+1
| | | | | | | | | | | | | | | | | | There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. The interface towards platforms and drivers will change to use one of CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called in the first stage with CBMEM available. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/mediatek: Fill coreboot table with PCIe infoJianjun Wang2022-05-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot table with PCIe info. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Demote log level of SPMI clock calibration problem to infoRex-BC Chen2022-05-091-2/+2
| | | | | | | | | | | | | | | | It's expected that the mismatch logs will be shown when doing calibration for spmi clock. If it is failed to do calibration for spmi clock for all data, the system will enter "die". Therefore, we adjust the log level from BIOS_ERR to BIOS_INFO. BUG=b:231531254 TEST=emerge-cherry coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/64090 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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