summaryrefslogtreecommitdiffstats
path: root/src/soc/mediatek
Commit message (Expand)AuthorAgeFilesLines
* mediatek/mt8183: Rename fields of struct sdram_paramsYu-Ping Wu2019-10-022-5/+4
* mediatek/mt8183: Allow modifying vcore voltageHsin-Hsiung Wang2019-10-012-0/+26
* mediatek/mt8183: Init SPM driverDawei Chien2019-09-303-49/+503
* mediatek/mt8183: Use different DRAM frequencies for eMCP DDRHuayang Duan2019-09-242-7/+27
* mediatek/mt8183: Support more DRAM frequency bootupHuayang Duan2019-09-205-781/+960
* mediatek/mt8183: Implement the dramc init settingHuayang Duan2019-09-207-1094/+1842
* cpu,mb,soc: Init missing lb_serial struct fieldsJacob Garber2019-09-191-1/+2
* mediatek/mt8183: Add soc ARM Trusted Firmware supportkenny liang2019-09-161-0/+2
* arm64: Uprev Arm TF and adjust to BL31 parameter changesJulius Werner2019-09-142-22/+0
* mediatek/mt8183: Add new option for eMCP DDRHuayang Duan2019-09-101-0/+7
* soc/mediatek: Fix USB enumeration issueChangqi Hu2019-09-062-0/+6
* mediatek/mt8183: postpone dcxo low power mode settingWeiyi Lu2019-09-043-3/+14
* mediatek/mt8183: Remove unnecessary parenthesesYu-Ping Wu2019-09-023-7/+7
* arm64: Rename arm_tf.c/h to bl31.c/hJulius Werner2019-08-301-1/+1
* mediatek/mt8183: add scp voltage initializationHsin-Hsiung Wang2019-08-212-0/+30
* mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE regionTristan Shieh2019-08-211-5/+5
* mediatek/mt8183: Overlap decompressor, verstage and romstageTristan Shieh2019-08-212-3/+3
* mediatek: Use GPIO based SPI CSYu-Ping Wu2019-08-214-8/+26
* arch/non-x86: Remove use of __PRE_RAM__Kyösti Mälkki2019-08-201-2/+0
* soc/mediatek: Change DSI init commands to take flexible length arrayHung-Te Lin2019-08-152-9/+22
* soc/mediatek/mt8183: Add DSI driverHung-Te Lin2019-08-157-2/+187
* soc/mediatek: dsi: Support sending MIPI init commandsHung-Te Lin2019-08-152-7/+138
* soc/mediatek: dsi: Refactor video timing calculationHung-Te Lin2019-08-154-11/+37
* soc/mediatek: dsi: Refactor PHY timing calculationHung-Te Lin2019-08-143-13/+83
* soc/mediatek: dsi: Refactor MIPI TX configurationHung-Te Lin2019-08-134-29/+41
* soc/mediatek: dsi: Unify format to bpp conversionHung-Te Lin2019-08-133-36/+37
* soc/mediatek: Create common DSI driver from mt8173Hung-Te Lin2019-08-135-459/+511
* soc/mediatek/mt8183: Add display controller driverYongqiang Niu2019-08-094-0/+314
* soc/mediatek/mt8173: Refactor display driver to share common partsHung-Te Lin2019-08-096-226/+248
* soc/mediatek/mt8173: Remove dual DSI modeHung-Te Lin2019-08-094-222/+52
* mediatek/mt8183: Add I2C driver codeQii Wang2019-08-075-0/+217
* mediatek: Refactor I2C code among similar SOCsQii Wang2019-08-025-335/+375
* soc/mediatek/mt8183: Init SSPMErin Lo2019-07-262-0/+7
* soc/mediatek: Use 'include <stdlib.h>' when appropriateElyes HAOUAS2019-07-252-2/+2
* mediatek/mt8183: Add md power-off flowYanjie Jiang2019-07-234-1/+59
* soc/mediatek/mt8183: Support SSPMErin Lo2019-07-224-0/+72
* mediatek/mt8183: Calibrate RTC eosc clockRan Bi2019-07-212-1/+196
* mediatek: Fill in input_hertz to coreboot tableTristan Shieh2019-07-112-1/+4
* arch/non-x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki2019-07-092-4/+0
* mediatek/mt8183: update dcxo output buffer settingWeiyi Lu2019-07-072-2/+4
* mediatek/mt8183: Enable RTC eosc calibration feature to save powerRan Bi2019-07-063-26/+33
* mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootupHuayang Duan2019-06-211-1/+1
* mediatek/mt8183: fix mode register setting fail issueHuayang Duan2019-06-211-45/+129
* mediatek/mt8183: enable DDR low power featuremtk111952019-06-216-53/+206
* mediatek/mt8183: set vproc12 voltage correctlyHsin-Hsiung Wang2019-06-211-1/+3
* mediatek/mt8183: Add infra group DCM settingWeiyi Lu2019-06-212-0/+15
* mediatek: Add SPI tick_dly settingMengqi Zhang2019-06-216-8/+25
* mediatek/mt8183: Add SPI GPIO driving settingMengqi Zhang2019-06-212-0/+58
* mediatek/mt8183: Support RTC in ramstageYou-Cheng Syu2019-06-211-0/+2
* mediatek/mt8183: Add efuse calibration in auxadcjg_poxu2019-06-213-1/+67
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 04:47:55 +0000