index
:
coreboot.git
24.02_branch
4.1
4.10_branch
4.11_branch
4.12_branch
4.14_branch
4.15_branch
4.16_branch
4.18_branch
4.19_branch
4.2
4.20_branch
4.22_branch
4.3
4.4
4.8_branch
classic-2014.10
coreboot-v1
coreboot-v3
main
master
rampayload
Coreboot firmware sources
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path:
root
/
src
/
soc
/
sifive
/
fu540
/
Makefile.inc
Commit message (
Expand
)
Author
Age
Files
Lines
*
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-11
1
-1
/
+0
*
src/: Replace GPL boilerplate with SPDX headers
Patrick Georgi
2020-05-09
1
-8
/
+1
*
soc: Remove copyright notices
Patrick Georgi
2020-03-18
1
-1
/
+0
*
soc/sifive/fu540: add code for spi and map flash to memory spaces
Xiang Wang
2019-08-12
1
-3
/
+3
*
soc/sifive/fu540: Simplify UART refclk calculation
Jonathan Neuschäfer
2018-12-03
1
-0
/
+1
*
riscv: add support smp_pause / smp_resume
Xiang Wang
2018-11-05
1
-0
/
+1
*
sifive/hifive-unleashed: enable CBMEM support
Philipp Hug
2018-09-15
1
-0
/
+1
*
soc/sifive/fu540: Switch clock to 1GHz in romstage
Philipp Hug
2018-09-14
1
-0
/
+2
*
soc/sifive/fu540: Makefile: include mtime_init in ramstage
Philipp Hug
2018-09-10
1
-0
/
+1
*
soc/sifive/fu540: Add driver for OTP memory
Philipp Hug
2018-09-10
1
-0
/
+2
*
soc/sifive/fu540: add CLINT support
Xiang Wang
2018-09-10
1
-1
/
+1
*
riscv: update mtime initialization
Xiang Wang
2018-09-10
1
-0
/
+1
*
sifive/fu540: add empty sdram init and size functions
Philipp Hug
2018-07-18
1
-0
/
+2
*
src/sifive: Add the SiFive Freedom Unleashed 540 SoC
Jonathan Neuschäfer
2018-04-26
1
-0
/
+33