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* arch/non-x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki2019-07-091-2/+0
* src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet ControllerXiang Wang2019-03-181-0/+35
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-044-4/+4
* riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCVRonald G. Minnich2019-01-241-1/+0
* riscv: create Kconfig architecture features for new partsRonald G. Minnich2019-01-171-0/+4
* console: Change BOOTBLOCK_CONSOLE default to `y`Nico Huber2019-01-141-1/+0
* riscv: fix non-SMP supportPhilipp Hug2018-12-071-1/+1
* soc/sifive/fu540: Add helper function to get tlclk frequencyJonathan Neuschäfer2018-12-053-5/+13
* soc/sifive/fu540: Load PLL settings from a structJonathan Neuschäfer2018-12-041-84/+72
* soc/sifive/fu540: Simplify UART refclk calculationJonathan Neuschäfer2018-12-033-5/+4
* riscv: add support smp_pause / smp_resumeXiang Wang2018-11-054-27/+11
* sifive/fu540: correct cbmem supportPhilipp Hug2018-10-302-2/+7
* soc/sifive/fu540: Document #if ENV_ROMSTAGE lineJonathan Neuschäfer2018-09-261-3/+2
* soc/sifive/fu540: Remove PLL parameters from sdram.cJonathan Neuschäfer2018-09-261-2/+0
* sifive/hifive-unleashed: enable CBMEM supportPhilipp Hug2018-09-151-0/+1
* soc/sifive: move ram_resource to mainboardPhilipp Hug2018-09-151-20/+0
* soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculationPhilipp Hug2018-09-141-1/+8
* soc/sifive/fu540: Initialize SDRAMPhilipp Hug2018-09-143-1/+240
* soc/sifive/fu540: Switch clock to 1GHz in romstagePhilipp Hug2018-09-142-16/+46
* soc/sifive/fu540: create ram_resource with actual memory sizePhilipp Hug2018-09-141-0/+20
* arch/riscv: provide a monotonic timerPhilipp Hug2018-09-141-0/+4
* soc/sifive/fu540: add SiFive supplied header files for SDRAM initializationPhilipp Hug2018-09-143-0/+1664
* soc/sifive/fu540: Get SDRAM controller out of resetPhilipp Hug2018-09-131-0/+34
* soc/sifive/fu540: Update clock settings according SiFive bootloaderPhilipp Hug2018-09-131-8/+30
* uart/sifive: make divisor configurablePhilipp Hug2018-09-132-1/+9
* soc/sifive/fu540: Initialize PLL and clockPhilipp Hug2018-09-122-0/+202
* soc/sifive: fix compiler warningPhilipp Hug2018-09-101-1/+1
* soc/sifive/fu540: Makefile: include mtime_init in ramstagePhilipp Hug2018-09-101-0/+1
* soc/sifive/fu540: Add driver for OTP memoryPhilipp Hug2018-09-103-0/+129
* soc/sifive/fu540: add CLINT supportXiang Wang2018-09-104-7/+42
* riscv: update mtime initializationXiang Wang2018-09-102-0/+23
* riscv: separately define stack locations at different stagesXiang Wang2018-09-021-2/+3
* sifive/fu540: add empty sdram init and size functionsPhilipp Hug2018-07-183-0/+59
* riscv: add support for modifying compiler optionsXiang Wang2018-07-171-0/+12
* src/sifive: Add the SiFive Freedom Unleashed 540 SoCJonathan Neuschäfer2018-04-269-0/+226
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