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* soc/intel/tigerlake: Enable USB2 port reset message on Type-C portsJohn Zhao2021-01-082-0/+5
* soc/amd/picasso: Generate GNB IO-APIC PCI routing tableRaul E Rangel2021-01-081-30/+100
* */Makefile.inc: Add some INTERMEDIATE targets to .PHONYArthur Heymans2021-01-081-0/+1
* cbfstool: Use flock() when accessing CBFS filesJulius Werner2021-01-081-1/+1
* soc/intel/jasperlake: Update acoustic noise related parametersMaulik V Vaghela2021-01-082-9/+21
* soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualificationKrishna Prasad Bhat2021-01-082-0/+16
* ACPI: Remove ACPI_NO_SMI_GNVSKyösti Mälkki2021-01-073-3/+0
* soc/amd/picasso: Add GRXS and GTXS methodEric Lai2021-01-072-46/+51
* soc/amd/picasso: Add STXS and CTXS methodEric Lai2021-01-072-41/+46
* arch/x86: Move prologue to .init sectionKyösti Mälkki2021-01-076-1/+20
* soc/intel/icelake: Remove unused ENABLE_DISPLAY_OVER_EXT_PCIE_GFXSubrata Banik2021-01-071-11/+0
* soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKUMatt DeVillier2021-01-071-1/+0
* soc/mediatek: rtc: Use `bool` as return typeYidi Lin2021-01-078-58/+61
* soc/intel/broadwell: Move MAX_CPUS from mb to SoCFelix Singer2021-01-061-0/+4
* soc/intel/skylake: Move MAX_CPUS from mb to SoCFelix Singer2021-01-061-0/+4
* soc/amd/picasso: Correctly populate the PCI interrupt line registerRaul E Rangel2021-01-063-0/+57
* soc/amd/picasso: Fix ACPI PCI routing tableRaul E Rangel2021-01-063-14/+158
* soc/amd/picasso/root_complex: add missing set_resourcesFelix Held2021-01-061-0/+1
* soc/amd/common/block/gpio_banks: fix sequence in gpio_outputFelix Held2021-01-061-1/+2
* soc/amd/common/block/gpio_banks: clear output enable in gpio_input_*Felix Held2021-01-061-2/+2
* soc/amd/common/block/gpio_banks: clear pull-up/down bits in gpio_inputFelix Held2021-01-061-1/+1
* soc/intel/alderlake: Update CPU microcode patch base address/sizeSubrata Banik2021-01-061-0/+11
* arch/x86: Pass GNVS as parameter to SMM moduleKyösti Mälkki2021-01-0411-113/+0
* soc/intel/baytrail/southcluster.asl: Use consistent comment formattingMatt DeVillier2021-01-041-23/+23
* soc/intel/baytrail: add LPEA resources to southcluster.aslMatt DeVillier2021-01-041-5/+28
* soc/intel/apollolake: Hook up GMA ACPI brightness controlsMatt DeVillier2021-01-043-0/+28
* soc/intel: Drop indirect <soc/nvs.h> includeKyösti Mälkki2021-01-0314-6/+8
* soc/intel: Replace <soc/nvs.h> with <soc/device_nvs.h>Kyösti Mälkki2021-01-034-4/+4
* sb,soc/intel: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki2021-01-031-6/+2
* soc/amd/picasso: Separate CPUID defs into new headerJason Glenesk2021-01-021-0/+1
* soc/intel/cnl: add panel and backlight configuration codeMichael Niewöhner2021-01-013-0/+69
* nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settingsMichael Niewöhner2021-01-016-84/+51
* soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representationMichael Niewöhner2021-01-012-11/+12
* soc/mediatek: dsi: Fix EoTp flagShaoming Chen2021-01-012-2/+15
* soc/intel/skylake: Remove device_nvs.hKyösti Mälkki2020-12-311-26/+0
* soc/mediatek/mt8192: Move flash_controller.c to common/Yidi Lin2020-12-3110-360/+66
* soc/mediatek/mt8192: Add DDR mode register initHuayang Duan2020-12-313-1/+408
* soc/mediatek/mt8192: Do dramc duty calibrationHuayang Duan2020-12-312-0/+79
* soc/mediatek/mt8192: Add dramc 8 phase calibrationHuayang Duan2020-12-313-0/+355
* soc/mediatek/mt8192: Update initial settings of dramcHuayang Duan2020-12-313-1/+625
* drivers/intel/gma: Include gfx.asl by default for all platforms...Matt DeVillier2020-12-304-0/+12
* soc/intel/common: Move gfx.asl to drivers/intel/gmaMatt DeVillier2020-12-308-13/+7
* soc/mediatek/mt8192: eint: unmask eint event mask registerG.Pangao2020-12-304-0/+33
* soc/intel/cnl: add Kconfig values for GMA backlight registersMichael Niewöhner2020-12-301-0/+12
* soc/intel: hook up new gpio device in the soc chipsMichael Niewöhner2020-12-3022-0/+76
* soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delayMichael Niewöhner2020-12-291-2/+2
* soc/intel/alderlake: Update chipset.cb for TCSS and USBEric Lai2020-12-292-6/+96
* soc/intel/skylake: Add 4 missing root ports to chipset dtFelix Singer2020-12-291-0/+4
* sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurableArthur Heymans2020-12-291-0/+17
* soc/mediatek/mt8192: Implement dramc base settings for each frequencyHuayang Duan2020-12-291-0/+2926
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