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* soc/amd/common/block/include/amdblocks/acpi.h: Add missing <types.h>Elyes HAOUAS2020-07-141-1/+1
| | | | | | | | | | BIT(x) needs <types.h> Change-Id: I5dc0d45567ae9879a7e12f2ccc48929d2abc9456 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* src: Drop unused <cpu/x86/tsc.h> includeElyes HAOUAS2020-07-145-5/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <cpu/x86/tsc.h>' -- src/) <(git grep -l 'TSC_SYNC\|tsc_struct\|rdtsc\|tsc_t\|multiply_to_tsc\|rdtscll\|tsc_to_uint64\|tsc_freq_mhz\|tsc_constant_rate' -- src/)|grep '<' Change-Id: Id090e232a96323adb8d9a24b81f7ae5669248f57 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42393 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS2020-07-148-8/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <cpu/x86/msr.h>' -- src/) <(git grep -l 'IA32_EFER\|EFER_\|TSC_MSR\|IA32_\|FEATURE_CONTROL_LOCK_BIT\|FEATURE_ENABLE_VMX\|SMRR_ENABLE\|CPUID_\|SGX_GLOBAL_ENABLE\|PLATFORM_INFO_SET_TDP\|SMBASE_RO_MSR\|MCG_CTL_P\|MCA_BANKS_MASK\|FAST_STRINGS_ENABLE_BIT\|SPEED_STEP_ENABLE_BIT\|ENERGY_POLICY_\|SMRR_PHYSMASK_\|MCA_STATUS_\|VMX_BASIC_HI_DUAL_MONITOR\|MC0_ADDR\|MC0_MISC\|MC0_CTL_MASK\|msr_struct\|msrinit_struct\|soc_msr_read\|soc_msr_write\|rdmsr\|wrmsr\|mca_valid\|mca_over\|mca_uc\|mca_en\|mca_miscv\|mca_addrv\|mca_pcc\|mca_idv\|mca_cecc\|mca_uecc\|mca_defd\|mca_poison\|mca_sublink\|mca_err_code\|mca_err_extcode\|MCA_ERRCODE_\|MCA_BANK_\|MCA_ERRTYPE_\|mca_err_type\|msr_set_bit\|msr_t\|msrinit_t' -- src/) |grep '<' Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41969 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/baytrail/northcluster.c: Add missing includeElyes HAOUAS2020-07-141-1/+1
| | | | | | | | | | Replace unused <stddef.h> with missing <stdint.h>. Change-Id: I85745c331c81a419cef4547fc1c67bde1e202e8f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43346 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/baytrail/romstage/pmc.c: Add missing includeElyes HAOUAS2020-07-141-1/+1
| | | | | | | | | | | Replace unused <stddef.h> with missing <stdint.h>. Change-Id: If8384f4fea66e26d7377311e7bd8379c7848a26f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43345 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/baytrail/romstage/raminit.c: Add missing includeElyes HAOUAS2020-07-141-1/+1
| | | | | | | | | | | Replace unused <stddef.h> with missing <stdint.h>. Change-Id: I659a067e3b737dc7efe5bdadfd88207cd4d7175d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43344 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/braswell/romstage/romstage.c: Add missing includeElyes HAOUAS2020-07-141-1/+1
| | | | | | | | | | | Replace unused <stddef.h> with missing <stdint.h>. Change-Id: I43b8ba5849de30e2ee253382ef85b17f2d0ae589 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43343 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/rockchip/rk3399/display.c: Add missing includeElyes HAOUAS2020-07-141-1/+1
| | | | | | | | | | Replace unused <stddef.h> with missing <stdint.h>. Change-Id: Ibdde8fb5ec5bf7d25facd78064a7837d24fa2c8a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43342 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Remove unused 'include <stdint.h>Elyes HAOUAS2020-07-1428-29/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Remove unused 'include <types.h>'Elyes HAOUAS2020-07-145-5/+1
| | | | | | | | | | | Files found using: diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: supply SMBIOS type 17Rob Barnes2020-07-132-0/+196
| | | | | | | | | | | | | | | | Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build SMBIOS type 17 tables. BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controllerMate Kukri2020-07-124-9/+21
| | | | | | | | | | | - Correctly detect device 17h as the MMC 4.5 controller - Support detection of the "old" MMC controller at device 10h Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/gpio: Convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE()Maxim Polyakov2020-07-121-3/+4
| | | | | | | | | | | | | | As with other macros, convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE() to make the code in gpio_defs.h cleaner. Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard does not change. Change-Id: Iadc9c4b3c96ae04c56d060cb060737a8eba7f165 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41034 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/gpio: Convert PAD_CFG0_RX_POL_* to PAD_RX_POL()Maxim Polyakov2020-07-121-3/+4
| | | | | | | | | | | | | | Converts PAD_CFG0_RX_POL_* macros to PAD_RX_POL() to make the code cleaner and reduce the length of the macro. Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard does not change. Change-Id: I09a048fd38ccb994f53c8829c549bc2b368fa546 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41033 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/gpio: Convert PAD_CFG0_TRIG_* to PAD_TRIG()Maxim Polyakov2020-07-121-9/+10
| | | | | | | | | | | | | | Converts PAD_CFG0_TRIG_ * macros to PAD_TRIG() to make the code cleaner and reduce the length of the macro, which is often used. Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 & T10-TNI carrierboard does not change. Change-Id: I9e1b4118fd6c6f0d58ee38a743aa8c27535f0dd9 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41032 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/pcie: Select ASPM on mainboard basisChristian Walter2020-07-121-2/+10
| | | | | | | | | | | | | | | | | | | | | Current the common soc code automatically selects PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE which breaks booting Windows with a PCIE NVIDIA graphics card attached on mainboards that do not have a CLKREQ# signal. This is commonly used on server and workstations boards where the additional power savings of L1 substate are not required. Make the PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE default y but do not select it anymore by the soc code, thus we can disable it in the mainboard code. Tested on CFL with Windows 10. Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41696 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp/cpx: use HOB_TYPE_GUID_EXTENSION to interpret platform HOBsJonathan Zhang2020-07-122-38/+25
| | | | | | | | | | | | | | | | | | | | | Platform HOBs (in particular IIO_UDS and MemoryMap HOBs) are of HOB type HOB_TYPE_GUID_EXTENSION, therefore they do not have resource structure. Remove the erroneous code related to resource structure. Remove unnecessary function prototypes from header files, and define them as static in hob_display.c. Since we have the HOB pointer, there is not need to search HOB by GUID. Remove unnecessary calling of fsp_find_extension_hob_by_guid(). Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: Ib99bce39e6eb2aeb95242dfba36774653bbe91fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/43335 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp: Add RTC failure checkingJingle Hsu2020-07-125-2/+33
| | | | | | | | | | | | | Add a weak function mainboard_rtc_failed() for mainboard customization. Check RTC_PWR_STS bit for RTC battery removal or CMOS clear jumper triggered event. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* vendocode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww28 release and adapt socJonathan Zhang2020-07-123-13/+23
| | | | | | | | | | | | | | | | | | | CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX. Also update IIO UDS HOB definition file accordingly. Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG. Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel is that they will converge to use FSPM_CONFIG over time. So both will co-exist for some time. Today coreboot common code expects FSP_M_CONFIG. Accomodate this situation in FspmUpd.h. The CPX-SP soc code is updated accordingly. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* soc/intel/tigerlake: Move tco_configure to bootblockTim Wawrzynczak2020-07-122-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | On ChromeOS systems with a serial-enabled BIOS and vboot writing a new firmware image to the Chrome EC, it was possible for the TCO watchdog timer to trip 2 times before tco_configure() was called in romstage. This caused an extra reboot of the system (at a rather inopportune time) and because the EC didn't perform a full reset, the system boots into recovery mode. This patch moves the call to tco_configure() for Tiger Lake from romstage to bootblock, in order to make sure the TCO watchdog timer is halted before vboot_sync_ec() runs in romstage. It should be harmless to configure the TCO device earlier in the boot flow. BUG=b:160272400 TEST=boot Volteer (to a non-recovery kernel!) with a freshly imaged EC Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iefdc2c861ab8b5fde7f736c04149be7de7b3ae0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43313 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Configure Type-C Input Output Manager(IOM) deviceJohn Zhao2020-07-121-0/+10
| | | | | | | | | | | | | | | | | | | | This adds Type-C Intel Input Output Manager(IOM) device with HID INTC1072. It provides MMIO range from 0xfbc10000 with size 0x1600. Intel Input Output Manager(IOM) kernel driver reads relevant information such as Type-C port status (whether a device is connected to a Type-C port or not) and the activity type on the Type-C ports (such as USB, Display Port, Thunderbolt) using this memory resource. BUG=b:156016218 TEST=Able to detect USB, TBT and USB4 on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ic733e831643bda6e052edf797ba0e6206eb4ddd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41762 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Add Type-C IOM base address and size macroJohn Zhao2020-07-121-0/+2
| | | | | | | | | | | | | | | | | | | | This adds Type-C IO Manageability engine base address and size. Tigerlake EDS(#575681) section 3.4.3 describes host bridge REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000. IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16). BUG=:b:156016218 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41759 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Add new IGD deviceRavi Sarawadi2020-07-122-0/+2
| | | | | | | | | | | | | | Add new IGD device ID for new Tigerlake SKU support. BUG=b:160394260 Branch=None TEST=build, boot and check IGD device is reported. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I1903d513b61655d0e939f80b0fd0108091fdd7e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
* arch/x86: Drop CBMEM_TOP_BACKUPKyösti Mälkki2020-07-114-3/+9
| | | | | | | | | | | | | Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCIRaul E Rangel2020-07-103-0/+58
| | | | | | | | | | | | | | | This provides the functionality to provide the GPE to the pci_xhci driver. BUG=b:154756391, b:160651028 TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and verify GPE is set. Resume using a USB keyboard. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/amd/picasso: Delete partially implemented usb implementationRaul E Rangel2020-07-105-129/+0
| | | | | | | | | | | | | | There is now a generic xhci driver we can use to generate the xHCI ACPI nodes. BUG=b:154756391 TEST=Boot trembyle and look at ACPI table Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41901 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Add missing include to smi.hRaul E Rangel2020-07-101-0/+1
| | | | | | | | | | | | | | | BUG=b:154756391 TEST=Don't see build failure. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I36b81643c29ec1e7978d521206fbc366060ab286 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43330 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Avoid NULL pointer dereferenceJohn Zhao2020-07-101-6/+6
| | | | | | | | | | | | | | | Coverity detects dereferencing a pointer that might be "NULL" when calling acpigen_write_scope. Add sanity check for scope to prevent NULL pointer dereference. Found-by: Coverity CID 1429980 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I6214fb83bccb19fe4edad65ce6b862815b8dcec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42837 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Add PCI driver for data fabric devicesFurquan Shaikh2020-07-102-1/+53
| | | | | | | | | | | | | | Data fabric devices are PCI devices which support PCI configuration space but do not require any MMIO/IO resources. This change adds a PCI driver for the data fabric devices which only provides device operations for adding node to SSDT and returning the ACPI name for the device. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/amd/picasso: Add driver for handling PCIE GPP bridgesFurquan Shaikh2020-07-103-36/+61
| | | | | | | | | | | | | | This change adds a driver pcie_gpp.c which provides device_operations for external and internal PCIe GPP bridges. These device operations include standard PCI bridge operations as well as operations for generating ACPI node for the device and returning appropriate ACPI name for it. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/amd/picasso: Map AOAC registers to enable i2c after S3Martin Roth2020-07-101-0/+6
| | | | | | | | | | | | | | | | When entering S3, zork shuts down the i2c controllers to save power. On resume, we need to re-enable i2c before accessing them, so we need to map the AOAC registers in verstage. BUG=b:160834101 TEST=psp_verstage works after resume. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43333 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definitionFelix Held2020-07-091-1/+1
| | | | | | | | | | | | | | | | | | The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it there. The soc/amd/* code itself uses the bit definition when accessing HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition. Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR, since that bit isn't in that MSR. TEST=Checked the code and the corresponding BKDG/PPR. Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43309 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/samsung/exynos5420: Drop dead codeAngel Pons2020-07-091-40/+0
| | | | | | | | | | | This code is not even being build-tested. Drop it before it grows moss. Change-Id: I4f06e5e8a0d25308ba56d09a3d8b71f04dbd27b7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/intel/broadwell/pcie.c: Drop dead codeAngel Pons2020-07-091-12/+0
| | | | | | | | | | | This code is not even being build-tested. Drop it before it grows moss. Change-Id: Ia314148abc900685d85aede3add480614fa8e99c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner
* soc/samsung/exynos5250: Drop dead codeAngel Pons2020-07-093-62/+0
| | | | | | | | | | | This code is not even being build-tested. Drop it before it grows moss. Change-Id: I4772680875b20308e57da073bbcdc4597aeed893 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43215 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Always load and run display opromRob Barnes2020-07-091-0/+2
| | | | | | | | | | | | | | | The kernel requires the display oprom is loaded and ran in order for the kernel to not panic. Therefore, select the correct settings such that normal mode works for Chrome OS. BUG=b:160560510 TEST=Boot Trembyle in developer mode and normal mode Change-Id: Ia6bcc99f8880a45818f959a957660c2c43b1bfdf Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/baytrail/pmutil.c: Constify string arraysAngel Pons2020-07-091-17/+16
| | | | | | | | | | | | This reduces the differences between Bay Trail and Braswell. The resulting binary changes, but it shouldn't matter. Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
* soc/intel/baytrail/pmutil.c: Do not hardcode num_bitsAngel Pons2020-07-091-9/+4
| | | | | | | | | | | This can result in accesses outside array bounds. Copy what Braswell does, which is slightly safer. Change-Id: If3d6f4e1f8921f0be7f4e5e438b7e73c46b8ef95 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
* soc/intel/baytrail: Align whitespace and commentsAngel Pons2020-07-0922-305/+331
| | | | | | | | | | | | This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* soc/intel/baytrail: Rename "pmc.h" to "pm.h"Angel Pons2020-07-0915-17/+17
| | | | | | | | | | | | This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* mainboard/intel/tglrvp: Remove unused PrmrrSize chip configSubrata Banik2020-07-092-11/+2
| | | | | | | | | | | | | | | Refer to commit 7736bfc TEST=Able to build and boot TGLRVP. Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/braswell: Drop some BIOS_SPEW printk'sAngel Pons2020-07-0911-73/+0
| | | | | | | | | | This reduces the differences between Bay Trail and Braswell. Change-Id: I60e4db72eed17cdeebd30b010f351e1ffc4187e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMANDAngel Pons2020-07-091-1/+1
| | | | | | | | | | | The PCI COMMAND register is 16 bits wide, so do not use 32-bit ops. Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
* soc/amd/picasso: Remove I2C4Edward Hill2020-07-093-48/+2
| | | | | | | | | | | | | | Remove I2C4 since it is a slave device used for USB-C mux control and should not be included with the other master devices. BUG=b:160624619 b:160292546 TEST=EC can communicate with AP mux I2C4 slave Change-Id: Idaad618e90d6264d881dc66628cf581a856c231d Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43263 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Add dummy spinlock for psp_verstageMartin Roth2020-07-091-0/+17
| | | | | | | | | | | | | | | | | If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the spinlock code is missing. Add dummy spinlock code as the spinlocks aren't needed in the PSP. TEST=Build with CONFIG_CMOS_POST enabled. BUG=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Update APOB size & base generationMartin Roth2020-07-081-6/+10
| | | | | | | | | | | | | | Make the APOB size & base generation the same as all the other command line arguments to amdfwtool. BUG=None TEST=Build & boot trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id78383d87bc98dd2c859c75585266411c226f950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* arch/x86: Add memmove.c to x86 bootblockMartin Roth2020-07-081-1/+0
| | | | | | | | | | | | | | | | This was specifically needed for vboot with psp_verstage, but adding it to always be built into bootblock if needed like memcpy & memset makes sense. TEST=Build & boot trembyle BUG=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* src/amd/common: Exclude biosram from psp_verstageMartin Roth2020-07-081-1/+1
| | | | | | | | | | | | | | This isn't needed for psp_verstage, and causes build failures if included. BUG=b:158124527 TEST=Build & boot Trembyle with psp_verstage Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I63942ad896d205c327d65bb8083da817b972962b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42808 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Halt if workbuf is absent after psp_verstageMartin Roth2020-07-081-0/+16
| | | | | | | | | | | | | Check for the workbuf in bootblock if psp_verstage is being used. BUG=b:158124527 TEST=Build & boot Trembyle with psp_verstage Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I0ec8d2c953bce4c44cde5102d2765e0ab9b5875e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42810 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common: Don't init SMIs or SCIs in psp_verstageMartin Roth2020-07-081-2/+10
| | | | | | | | | | | | | We can't set the SMI or SCI flags in psp verstage, so skip them. TEST=Build BUG=b:154142138 Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42765 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 07:35:52 +0000