summaryrefslogtreecommitdiffstats
path: root/src/soc
Commit message (Collapse)AuthorAgeFilesLines
* soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7Varshit Pandya2024-02-241-1/+1
| | | | | | | | | | | | Glinda started as a copy of mendocino and GPP_CLK_OUTPUT_AVAILABLE was not updated. GPP_CLK_OUTPUT_AVAILABLE should be 7 as per Processor Programming Reference (PPR) (#57254), table "GPP ClkREQB Mapping". Change-Id: I26e9dea58b2ddf5cbedbcccb8bcbc5f9efab3165 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80701 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/acp: use clrsetbits32p to avoid need for castsFelix Held2024-02-232-2/+2
| | | | | | | | | | | Use clrsetbits32p instead of clrsetbits32 to not need to cast the uintptr_t address to void * in the function call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic29bf04866a7e1d5c831422f31803a724a41069b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/amd/glinda: Use gpp_clk_setup_common functionVarshit Pandya2024-02-233-53/+2
| | | | | | | | | | | In follow up to commit 0452d0939e7d ("soc/amd: Factor out gpp_clk_setup function") use gpp_clk_setup_common for glinda as well. Change-Id: If0c1cda0d36de48c7f7315a1b8203b0e53f63f75 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80699 Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* arch/x86/ioapic: use uintptr_t for IOAPIC base addressFelix Held2024-02-238-13/+13
| | | | | | | | | | | | | | | Use uintptr_t for the IOAPIC base parameter of the various IOAPIC- related functions to avoid needing type casts in the callers. This also allows dropping the VIO_APIC_VADDR define and consistently use the IO_APIC_ADDR define instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I912943e923ff092708e90138caa5e1daf269a69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_configVarshit Pandya2024-02-233-6/+7
| | | | | | | | | | | | | | | This function turns off gpp_clk for the devices which are disabled, and adds the code to fix up the clock configuration depending on dxio descriptors. Also this brings glinda in line with cezanne, mendocino, phoenix and picasso. This also prepares glinda to use the common function gpp_clk_setup_common. Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80415 Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/adl: Set slp-s0 counter frequencyMarx Wang2024-02-231-0/+5
| | | | | | | | | | | | | | | | | System sleep time (SLP_S0 signal asserted) is measured in ticks, for Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks. BUG=b:301854636 TEST=/sys/devices/system/cpu/cpuidle/ low_power_idle_system_residency_us" will show system idle residency time Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/xeon_sp: Locate PCI devices by Ven/Dev IDPatrick Rudolph2024-02-231-35/+44
| | | | | | | | | | | | | | | | | Since the ACPI code is looking for VtdBars, that only appear on Vtd devices, search for the Vtd device in devicetree. With the previous commit the VtdBar is now exposed as a resource on the Vtd device and thus can easily be accessed and used. Drop the FSP HOB parsing and just use coreboot native functions. Allows the code to work with multiple PCI segment groups. Change-Id: I2c752dc595ac4c901f2b3a96718e256e413c76a7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
* soc/intel/xeon_sp: Add helper functionsPatrick Rudolph2024-02-232-0/+83
| | | | | | | | | | | | | | | | | | Provide a helper function to locate PCI devices on a given socket by their PCI vendor and device IDs and functions to return information about the current device, like the corresponding stack and socket. In addition add functions to return "location" information, like stack and socket affiliation. This becomes handy when locating devices and generating ACPI code. Change-Id: I266360588548ba579f46b228c4d5b3ae6e39a029 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80094 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/xeon_sp/uncore: Read VtdBarPatrick Rudolph2024-02-234-4/+19
| | | | | | | | | | | | | | Read the VtdBar and add it to the resources of the host bridge PCI device. The BAR is already marked as PciResourceMem32 in the parent PCI domain. This allows easy probing for VTD devices with enabled VtdBars in the next commit, without the need to look up the stack HOB. Change-Id: Id579a94e653473f3dd0dccea6e33dc64f792d028 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/common/lpc: Skip setting resources for disabled devicesMatt DeVillier2024-02-221-0/+3
| | | | | | | | | | | | | | | | | If a downstream LPC device (eg, SIO function) is disabled, we shouldn't attempt to open PMIO windows for it, as those functions often have unset IO bases (which default to 0), resulting in false errors like: [ERROR] LPC IO decode base 0! TEST=build/boot purism/librem_cnl (Mini v2), verify no LPC IO errors in cbmem log for disabled SIO functions. Change-Id: I92c79fc01be21466976f3056242f6d1824878eab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/braswell/gpio_support: drop unused get_gpioFelix Held2024-02-222-6/+0
| | | | | | | | | | | The get_gpio function in this file is both unused and it shouldn't use a signed int to pass in the MMIO base address and offset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b08bad040ad175b37175ef21d0a0a29525c4478 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/intel/xeon_sp: Print device path when reporting resourcesPatrick Rudolph2024-02-221-2/+2
| | | | | | | | | | | | As there are multiple Vtd devices, print the path of each when reporting resource registers. Change-Id: I5d3a6484ed7c7b9760fce0f3a02a15ca26c2cbd2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80549 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
* soc/intel/xeon_sp: Align resources to 4KPatrick Rudolph2024-02-222-3/+2
| | | | | | | | | | | | | | | | | | | | | | The lower bit of the BAR might be used for something else, like enable bits, so mask the lower 12 bits and align all base address to 4K. Confirmed that all BARs have a minimum alignment of 4K, so that masking the lower bits doesn't change the reported address. The alignment of the VTD BARs is: - VTD_MMCFG_BASE_CSR 64 MiB - VTD_MMIOL_CSR 1 MiB - VTD_NCMEM_BASE_CSR 64 MiB - VTD_TSEG_BASE_CSR 1 MiB - VTD_BAR_CSR 4 KiB Change-Id: I9a7b963c0074246616968dd15c147f4916297d59 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/xeon_sp: Refactor IOAT compiler optimization outsShuo Liu2024-02-222-9/+2
| | | | | | | | | | | | | | | | | IOAT logics are optimized out for non-IOAT platforms where CONFIG(HAVE_IOAT_DOMAINS) as false. This patch puts CONFIG(HAVE_IOAT_DOMAINS) check together ahead of is_ioat_iio_stack_res() check in the corresponding if statement to fulfill the optimization outs. TEST=intel/archercity CRB Change-Id: I2d16c6ff5320bc9195a1033b6d55e3d997b19b88 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80683 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Remove Alder Lake M SKUSean Rhodes2024-02-225-33/+2
| | | | | | | | | | | ADL-M is not commercially available, so it can be removed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/alderlake: Sync UPD Usb4CmMode with KconfigSean Rhodes2024-02-221-0/+4
| | | | | | | | | | | | | | | The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will time out. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/ocp/*: Remove unused ACPI opregionArthur Heymans2024-02-211-1/+1
| | | | | | | | | | | | The base for this region is a magic number and none for the fields are used, which likely means this was simply copied from a different firmware. Change-Id: I217bbd0b098cd15ef296854cc6262d651f11d10e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73183 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Include ADL-N ID 5Sean Rhodes2024-02-211-0/+2
| | | | | | | | | | This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI headerShuo Liu2024-02-201-0/+3
| | | | | | | | | | | | | | | Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC are ACPI table specific, and could be used across Xeon-SP SoCs. This patch moves their definition from FSP header to Xeon-SP layer ACPI header. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80629 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp: Use ACPI common flags in SRAT generationShuo Liu2024-02-201-2/+2
| | | | | | | | | | | | | | Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common codes. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* soc/intel/xeon_sp: Add support for is_ioat_iio_stack_resShuo Liu2024-02-205-18/+25
| | | | | | | | | | | | | | | | IOAT is the term for the on-chip accelerator technology of Xeon-SP. In CPX and SPR, IOAT stack is also named as DINO stack. Different SoC has different check criteria for IOAT stacks, this patch introduces an util function to abstract these differences as well as cleaning up the usage of names. TEST=intel/archercity CRB Change-Id: I376928ad89b68b294734000678dad6f070d3c97d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80578 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier2024-02-191-0/+1
| | | | | | | | | | | | | Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/alderlake: Include ADL-N ID 5 0x4618Sean Rhodes2024-02-195-0/+6
| | | | | | | | | | This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/common: Add ADL_N ID 5 0x4618Sean Rhodes2024-02-191-0/+1
| | | | | | | | | | This patch adds ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/80487 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Drop redundant PcieRpEnableNico Huber2024-02-193-7/+4
| | | | | | | | | | | | | | | The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/jasperlake: Drop redundant PcieRpEnableNico Huber2024-02-196-14/+26
| | | | | | | | | | | | | | | | The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp/spr: Don't leak memoryPatrick Rudolph2024-02-183-10/+10
| | | | | | | | | | | | | | | | | Only call fill_pds() once to prevent leaking memory. Previously it was called for every active stack on every socket. Only call dump_pds() once to prevent spamming the console with the same information. Drop the return value since it's always returning success. Change-Id: Ifa9609e9da086dc9731556014ea9b320b270d776 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/xeon_sp/uncore: Don't print uninitialized memoryPatrick Rudolph2024-02-181-0/+8
| | | | | | | | | | | | | | | | The struct map_entry has two zero'd entries due to the ifdef being used. Do not read those entries and do not print those entries. Fixes a NULL string being printed along as the vendor and device ID of the PCI device. Change-Id: Id87ced76af552c0d064538f8140d1b78724fb833 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80546 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/mtl: Skip RW CBFS ucode update if RO is lockedSubrata Banik2024-02-181-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch eliminates coreboot from loading microcode from RW CBFS (when the RO descriptor is locked, which indicates a fixed RO image) because the kernel can already patch the microcode on BSPs and APs while booting to OS. This may be a chance to lower the burden on the AP FW side because patching microcode on in-field devices is subject to firmware updates, which are rarely published and, if required, must go through the firmware qualification testing procedure (which is costly, unlike kernel updates for ucode updates). 1. The FIT loads the necessary microcode from the RO during reset. 2. Reloading microcode from RW CBFS impacts boot time (~60ms, core-dependent). 3. The kernel can still load microcode updates. ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is sufficient for initial boot, and the kernel can apply updates later. BUG=none TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode loading when RO is locked. Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
* soc/intel/jasperlake: select SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier2024-02-181-0/+1
| | | | | | | | | | | | | Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I8ebb915fbc21f82e39304473b0fcaa620559b5d5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80558 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/dtt: Add ACPI stub for TCPU deviceMatt DeVillier2024-02-181-0/+25
| | | | | | | | | | | | | | | | | | | | Add an ACPI stub containing the TCPU device in proper scope, along with the device status, on boards not using the DPTF driver, so that there exists an ACPI device to be referenced from the PEPD LPI constraint list. Adding the stub fixes an AE_NOT_FOUND ACPI error under Linux for _SB.PCI0.TCPU on boards with the SA thermal device enabled but which do not use the Intel DPTF driver. TEST=build/boot Linux,Win11 on purism/librem_cnl (Librem Mini v2). Change-Id: I926d0461e5e0dfaf606102575c2be555a6bfb695 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/alderlake/acpi: Drop ACPI stub for SATA deviceMatt DeVillier2024-02-182-10/+0
| | | | | | | | | | | This is now generated by acpigen in the common/block/sata module. Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/common/block/sata: Fix scope for SATA ACPI deviceMatt DeVillier2024-02-181-1/+1
| | | | | | | | | | | | | | | | | | | | | acpi_device_path() includes the device name, so we end up with: Scope (\_SB.PCI0.SATA) { Device (SATA) { ... Fix this by using acpi_device_scope() instead. TEST=build/boot purism librem_cml (Mini v2), dump ACPI and verify SATA device scope correct. Change-Id: Ibbc8890d93b22f0ecba4b3a9b0531994574b3d55 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80554 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc: Add SPDX license headers to Kconfig filesMartin Roth2024-02-18122-0/+241
| | | | | | | | | | Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intelblocks/systemagent: Add missing N6005 Jasper Lake SKU to PCI ID listMichał Żygowski2024-02-171-0/+1
| | | | | | | | Change-Id: I3fb4c6cfe24290c34682ff1c3396540465048727 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/jasperlake/bootblock: Report missing Jasper Lake SKUMichał Żygowski2024-02-171-0/+1
| | | | | | | | Change-Id: Ie0d25eca75225ab33e6c15ef5ccb9073151f4148 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/mtl: Double the `IgdDvmt50PreAlloc` UPD size to 128MBSubrata Banik2024-02-161-2/+2
| | | | | | | | | | | | | | This patch increases the IgdDvmt50PreAlloc value as per Intel recommendation starting with GFX PEIM 103x. TEST=Able to build and boot google/rex. Change-Id: I236b38a1ac5efbfcd23e373c09204d8a07b97618 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80406 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/common/tcss: Rename tcss_mux_init to disconnect_tcss_devicesSean Rhodes2024-02-151-2/+2
| | | | | | | | | | | | | | Rename tcss_mux_init to disconnect_tcss_devices to make it clear what this function is doing, as it doesn't initialise anything. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5e43f0cca9d49bc30fc189663490a306efd71584 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79874 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* tree; Remove unused <lib.h>Elyes Haouas2024-02-141-1/+0
| | | | | | | | | Change-Id: Ifa5c89aad7d0538c556665f8b4372e44cf593822 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80433 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Leverage IA common code for range calculationsSubrata Banik2024-02-132-126/+4
| | | | | | | | | | | | | | | | Improves code maintainability and potentially reduces redundancy by using the IA common implementation. Additionally, drop the unused macros from SoC local. TEST=Build and boot successful on google/marasov. Change-Id: I290fea99f04cfc9f18e5f1435ed07de42995869f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80403 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Leverage IA common code for range calculationsSubrata Banik2024-02-132-126/+4
| | | | | | | | | | | | | | | | | Improves code maintainability and potentially reduces redundancy by using the IA common implementation. Additionally, drop the unused macros from SoC local. TEST=Build and boot successful on google/screebo. Change-Id: Ie0baae1d3b0093389649dee3531902c5e86c02fe Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80404 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/cmn/sa: Add APIs into System Agent (SA) common codeSubrata Banik2024-02-133-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit streamlines code and strengthens common code robustness by moving the following SoC-layer functions to the common layer: - sa_get_mmcfg_size: Retrieves the MMIO (Memory-Mapped I/O) configuration space size by reading offset 0x60 of the PCI Host Bridge (D0:F0). - sa_get_dsm_size: Calculates the size of the DSM (Device Stolen Memory) by reading offset 0x50 of the PCI Host Bridge (D0:F0) to determine pre-allocated memory for the IGD (Integrated Graphics Device). - sa_get_gsm_size: Calculates the size of the GSM (Graphics Stolen Memory) by reading offset 0x52 of the PCI Host Bridge (D0:F0). - sa_get_dpr_size: Determines the size of the DMA Protection Range (DPR) by reading offset 0x5C of the PCI Host Bridge (D0:F0). TEST= Build and boot successful on google/screebo. Change-Id: Ic00e001563ec6f0d737a445964c716b45db43327 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/amd/picasso: Use gpp_clk_setup_common functionVarshit Pandya2024-02-123-53/+2
| | | | | | | | | | In follow up to CB:80285 use gpp_clk_setup_common for picasso as well. Change-Id: I68d498d08d5975037086c84ff2f7fdb265ee84d9 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80414 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_configVarshit Pandya2024-02-123-6/+7
| | | | | | | | | | | | | | | This function turns off gpp_clk for the devices which are disabled, and adds the code to fix up the clock configuration depending on dxio descriptors. Also this brings picasso in line with cezanne, mendocino and phoenix. This also prepares picasso to use the common function gpp_clk_setup_common. Change-Id: Ice2e3a5a78359da9a438434c7d4aa1eca878d396 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80413 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/intel/cmn/sa: Refactor SA common codeSubrata Banik2024-02-126-41/+32
| | | | | | | | | | | | | | | | | | Leverages common SA header definitions for Host Bridge registers. Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity. Additionally, made some minor code alignment corrections while adding newer macros in the header file. TEST= Build and boot successful on google/screebo. Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
* soc/amd: Factor out gpp_clk_setup functionVarshit Pandya2024-02-1013-160/+80
| | | | | | | | | | | | | | | | gpp_clk_setup code in most AMD SoC is similar and it can moved to common code. The only thing which is SoC dependent in this function is the SoC config, hence keep it in SoC code and move everything else in new gpp_clk_setup_common function which is in soc/amd/common. Picasso and Glinda don't have pcie_gpp_dxio_update_clk_req_config fixup function so they are addressed in later patches. Change-Id: I7d7da4bfe079f07e31212247dbf3acd14daa6447 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80285 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/acpi: Pass struct device to acpi_create_srat_gia_pciPatrick Rudolph2024-02-091-11/+5
| | | | | | | | | | | | | | Instead of S:B:D:F numbers pass the struct device to acpi_create_srat_gia_pci and let it extract the information needed. This also adds support for PCI multi segment groups. Change-Id: Iafe32e98f0c85f14347695ccaa0225e43fad99e7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80258 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp/numa: Store pointer to devicePatrick Rudolph2024-02-095-8/+9
| | | | | | | | | | | Instead of a BDF number store a pointer to the device itself. Change-Id: I3fef93c5e54c8af792102bcd25364c43b554a5f0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/amd/common/data_fabric/domain: drop unneeded parenthesisFelix Held2024-02-081-1/+1
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I84a7b7b1b2c45b773c6f10b39e7813db3f96546e Reviewed-on: https://review.coreboot.org/c/coreboot/+/80408 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/data_fabric/domain: don't report DRAM as MMIO producerFelix Held2024-02-081-0/+3
| | | | | | | | | | | | | | | | | | | | In commit 30f36c35e75a ("soc/amd: rework DRAM and fixed resource reporting") the reporting of the DRAM resources was moved from the northbridge PCI device to the domain device. amd_pci_domain_fill_ssdt didn't skip those DRAM resources when generation the resource producer ranges which made Windows 10 very unhappy when it tried to evaluating the ACPI tables causing it to reboot in a loop. To fix this, add a check to also skip the resources that have the IORESOURCE_STORED flag set when generating the resource producer ranges for the PCI root. TEST=Windows 10 now successfully boots and reboots again on Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b6d3fd8c7f89aa4364de7963d745aef8d6b6f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80407 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-30 10:57:04 +0000