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* src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-06-044-4/+5
* soc/{amd,intel}: Use postcar_frame_add_romcache()Nico Huber2018-06-046-14/+7
* soc/intel/denverton_ns: Get rid of device_tElyes HAOUAS2018-06-0410-36/+38
* soc/intel/skylake: Get rid of device_tElyes HAOUAS2018-06-048-21/+21
* soc/intel/apollolake: Get rid of device_tElyes HAOUAS2018-06-042-7/+7
* soc/intel/braswell: Get rid of device_tElyes HAOUAS2018-06-0417-57/+62
* soc/intel/fsp_broadwell_de: Get rid of device_tElyes HAOUAS2018-06-0410-35/+37
* soc/intel/fsp_baytrail: Get rid of device_tElyes HAOUAS2018-06-0413-50/+50
* soc/intel/apollolake: Add Page table mapping for System MemoryHannah Williams2018-06-033-47/+1670
* soc/intel/common: Add edge trigger configuartion for IOAPIC IRQ modeAamir Bohra2018-06-021-0/+3
* soc/intel/cannonlake: Get rid of device_tElyes HAOUAS2018-06-016-10/+10
* soc/intel/broadwell: Get rid of device_tElyes HAOUAS2018-06-0112-65/+68
* soc/amd/stoneyridge: Add ACPI device name lookupMarc Jones2018-06-011-0/+12
* soc/intel/broadwell: decouple PEI memory struct from coreboot headerMatt DeVillier2018-05-312-4/+108
* soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)Nico Huber2018-05-316-9/+9
* {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber2018-05-311-2/+1
* soc/intel/skylake: Select common P2SB codeSubrata Banik2018-05-313-22/+24
* soc/intel/cannonlake: Enable IDT and expection handling support for all stagesAamir Bohra2018-05-301-0/+1
* src/soc: Add and update license headersMartin Roth2018-05-2946-253/+416
* fsp_broadwell_de: Select TSC_MONOTONIC_TIMER by defaultDavid Hendricks2018-05-281-0/+1
* intel/skylake: nhlt: Update Max98373's capture formatSathyanarayana Nujella2018-05-281-2/+2
* soc/intel/quark: Get rid of device_tElyes HAOUAS2018-05-286-7/+7
* soc/qualcomm: Get rid of device_tElyes HAOUAS2018-05-283-9/+9
* soc/nvidia: Get rid of device_tElyes HAOUAS2018-05-287-11/+11
* soc/intel/cannonlake: Select common XHCI codeSubrata Banik2018-05-273-1/+5
* grunt: Wire up the EC SMI handlerRaul E Rangel2018-05-271-0/+1
* amd: Don't call halt() when in SMMRaul E Rangel2018-05-271-1/+8
* stoneyridge GPIO: Create and use PAD_INT for interrupt pinsRichard Spiegel2018-05-275-58/+395
* soc/amd/stoneyridge: Increment boot_count on non-S3 bootsDaniel Kurtz2018-05-251-0/+3
* soc/amd/stoneyridge: Record ACPI Wake events in ELOGDaniel Kurtz2018-05-251-0/+4
* soc/intel/cannonlake: Reduce STACK_SIZE to 4KiBSubrata Banik2018-05-251-4/+0
* soc/intel/baytrail: Get rid of device_tElyes HAOUAS2018-05-2418-62/+68
* src: Remove space after `defined`Elyes HAOUAS2018-05-241-3/+3
* mb/google/kahlee/dsdt.asl: Add method _SWSRichard Spiegel2018-05-231-0/+32
* stoneyridge: Store wake parameters in NVSRichard Spiegel2018-05-232-0/+39
* soc/amd/common/block/pci: Get rid of device_tElyes HAOUAS2018-05-231-2/+2
* soc/amd/stoneyridge/: Get rid of device_tElyes HAOUAS2018-05-238-39/+39
* soc/intel/apollolake: Bypass FSP's CpuMemorytest, PCIe pwr seq & SPI InitSrinidhi N Kaushik2018-05-222-9/+21
* soc/nvidia/tegra(124|210): Add distclean targetsMartin Roth2018-05-222-2/+2
* amd/stoneyridge: Increase SMM reserved memoryMarshall Dawson2018-05-221-1/+1
* src: Remove non-ascii charactersMartin Roth2018-05-225-16/+16
* rk3399: Enable bootblock compressionJulius Werner2018-05-226-8/+8
* bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner2018-05-226-6/+6
* cpu/x86: Add support to run function on single APSubrata Banik2018-05-191-2/+4
* soc/intel/cannonlake: Add CONFIG_SMM_RESERVED_SIZE configSubrata Banik2018-05-191-0/+4
* soc/amd/stoneyridge: Support ACPI USB code generationDuncan Laurie2018-05-184-2/+52
* soc/intel: Add support for USB ACPI code generationDuncan Laurie2018-05-185-1/+100
* soc/intel/skylake: Fix AP timeout issue while executing sgx_configureSubrata Banik2018-05-171-2/+3
* soc/intel/skylake: check DPTF_TSR1_ACTIVE_AC* in _ACx methodsJohn Su2018-05-151-0/+33
* soc/intel/apollolake: add rt5682 NHLT supportNaveen Manohar2018-05-154-0/+67
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