| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | soc/intel/tigerlake: Add mainboard hook for overriding SoC config | Jes Klinke | 2020-09-02 | 2 | -0/+7 |
| * | src: Drop redundant 'select BOOTBLOCK_CONSOLE' | Elyes HAOUAS | 2020-09-02 | 2 | -2/+0 |
| * | soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE' | Elyes HAOUAS | 2020-09-02 | 1 | -2/+0 |
| * | {nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a) | Elyes HAOUAS | 2020-09-02 | 1 | -1/+1 |
| * | {include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent | Subrata Banik | 2020-09-01 | 8 | -18/+18 |
| * | soc/intel/elkhartlake/romstage: Do initial SoC commit till romstage | Tan, Lean Sheng | 2020-08-31 | 8 | -0/+293 |
| * | soc/intel/elkhartlake/bootblock: Do initial SoC commit until bootblock | Tan, Lean Sheng | 2020-08-31 | 13 | -0/+874 |
| * | soc/amd/picasso/southbridge: make GPP clock outputs configurable | Felix Held | 2020-08-31 | 3 | -0/+54 |
| * | soc/amd/picasso/southbridge.h: rename GPP clock setting offsets | Felix Held | 2020-08-31 | 1 | -6/+8 |
| * | soc/amd/picasso/southbridge.h: replace GPP_CLK_REQ_MAP_* with macros | Felix Held | 2020-08-31 | 1 | -12/+5 |
| * | soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitions | Felix Held | 2020-08-31 | 1 | -2/+0 |
| * | {intel/gma,include/device}: Delete unused 'drm_dp_helper.h' file | Elyes HAOUAS | 2020-08-31 | 1 | -1/+0 |
| * | PCI IDs: Add PCI ID for CML DPTF/DTT PCI device | Edward O'Callaghan | 2020-08-29 | 1 | -0/+1 |
| * | amd/picasso/psp_verstage: add vboot rsa function | Kangheui Won | 2020-08-28 | 2 | -0/+53 |
| * | soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabled | Matt Papageorge | 2020-08-28 | 1 | -0/+24 |
| * | vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt soc | Jonathan Zhang | 2020-08-28 | 1 | -10/+4 |
| * | soc/intel/tigerlake: add ddr4-spd-empty.hex | Aaron Durbin | 2020-08-28 | 1 | -0/+32 |
| * | mb/google/zork: Switch zork to use spd_tools | Rob Barnes | 2020-08-28 | 1 | -26/+3 |
| * | util: Add memory parts needed by zork boards | Rob Barnes | 2020-08-28 | 7 | -0/+203 |
| * | util/gen_spd: translate DeviceBusWidth to die bus width | Nick Vaccaro | 2020-08-28 | 1 | -1/+1 |
| * | soc/mediatek/mt8192: Use SPI-NOR as flash controller | CK Hu | 2020-08-28 | 4 | -0/+265 |
| * | util: rename lp4x spds to include "lp4x-" in name | Nick Vaccaro | 2020-08-28 | 12 | -0/+0 |
| * | util: volteer/dedede: move generic SPDs to common location | Nick Vaccaro | 2020-08-28 | 19 | -28/+28 |
| * | symbols: Change implementation details of DECLARE_OPTIONAL_REGION() | Julius Werner | 2020-08-27 | 1 | -2/+0 |
| * | soc/intel/common: Include Elkhart Lake SA IDs | Tan, Lean Sheng | 2020-08-27 | 1 | -0/+11 |
| * | soc/intel/common: Add Elkhart Lake B0 CPU ID | Tan, Lean Sheng | 2020-08-27 | 2 | -0/+2 |
| * | soc/mediatek: Include addressmap.h in gpio_common.h | CK Hu | 2020-08-26 | 1 | -0/+1 |
| * | soc/intel/tigerlake: Rename pch_init() code | Alexey Buyanov | 2020-08-26 | 6 | -6/+6 |
| * | util: Add spd_tools to generate DDR4 SPDs for TGL boards | Nick Vaccaro | 2020-08-25 | 3 | -0/+67 |
| * | soc/amd/picasso: If psp_verstage is in RO, don't reset on error | Martin Roth | 2020-08-25 | 1 | -8/+14 |
| * | soc/mediatek/mt8192: Add dramc param struct | Huayang Duan | 2020-08-25 | 3 | -0/+294 |
| * | soc/intel/jasperlake: Disable multiphase SI init | Ronak Kanabar | 2020-08-25 | 1 | -0/+6 |
| * | soc/intel/jasperlake: Select PLATFORM_USES_FSP2_2 | Ronak Kanabar | 2020-08-25 | 1 | -1/+1 |
| * | soc/amd/picasso: Reboot for recovery if no psp workbuf is found | Martin Roth | 2020-08-24 | 6 | -2/+51 |
| * | mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms | Shelley Chen | 2020-08-24 | 4 | -32/+35 |
| * | soc/amd/common: Move interrupt and wake status clear | Josie Nordrum | 2020-08-24 | 1 | -3/+2 |
| * | soc/intel/jasperlake: Run pmc_set_acpi_mode() during .init in pmc_ops | Kane Chen | 2020-08-24 | 1 | -2/+15 |
| * | soc/amd/picasso: Add console & timestamp buffers to psp_verstage | Martin Roth | 2020-08-24 | 5 | -22/+93 |
| * | soc/intel/tigerlake: Fix IPU and Vtd config | Ravi Sarawadi | 2020-08-24 | 1 | -4/+15 |
| * | soc/intel/jasperlake: use UDK_202005_BINDING | Ronak Kanabar | 2020-08-24 | 1 | -1/+1 |
| * | soc/sifive: Drop unneeded empty lines | Elyes HAOUAS | 2020-08-24 | 5 | -18/+0 |
| * | soc/amd/picasso: Store ddr_frequency in MT/s | Rob Barnes | 2020-08-24 | 1 | -1/+9 |
| * | soc/intel/common: Add downgrade support for CSE Firmware | Sridhar Siricilla | 2020-08-24 | 2 | -3/+92 |
| * | soc/amd/picasso/romstage: Set HDA disable UPD if controller disabled | Felix Held | 2020-08-23 | 1 | -0/+27 |
| * | soc/intel/cnl: Configure FSP option PcieRpSlotImplemented | Nico Huber | 2020-08-23 | 2 | -0/+4 |
| * | soc/amd/picasso: If using VBOOT, skip the APOB_NV region for RO | Martin Roth | 2020-08-21 | 1 | -2/+11 |
| * | soc/amd/common: add rudimentary ATIF support | Aaron Durbin | 2020-08-21 | 2 | -0/+109 |
| * | SMM: Validate more user-provided pointers | Patrick Rudolph | 2020-08-21 | 4 | -0/+20 |
| * | soc/intel/tigerlake: Enable long cr50 ready pulses | Jes Klinke | 2020-08-21 | 1 | -0/+5 |
| * | soc/intel/apollolake: Select HAVE_ASAN_IN_ROMSTAGE | Harshit Sharma | 2020-08-21 | 1 | -0/+1 |
