summaryrefslogtreecommitdiffstats
path: root/src/soc
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/alderlake: Drop unreferenced `InternalGfx`Angel Pons2021-04-101-1/+0
* soc/intel/alderlake: Skip D3Cold for TBTSubrata Banik2021-04-101-0/+6
* mb/ocp/deltalake: Override DDR frequency limit via VPD variableTim Chu2021-04-091-0/+15
* mb/google/asurada: select mmc storage configWenbin Mei2021-04-091-0/+1
* soc/mediatek: add new driver 'msdc' for eMMCWenbin Mei2021-04-092-0/+657
* soc/amd: remove special GPIO_2 override soc_gpio_hookKyösti Mälkki2021-04-085-36/+0
* soc/mediatek: dsi: fine tune the delta time for EoTpJitao Shi2021-04-081-1/+1
* soc/intel/dnv_ns: hook up new gpio device operationsMichael Niewöhner2021-04-082-0/+4
* soc/qualcomm: move code to commonRavi Kumar Bokka2021-04-087-114/+39
* soc/amd/common: Add PM_ESPI_INTR_CTRLRaul E Rangel2021-04-081-0/+2
* soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd`Angel Pons2021-04-082-14/+0
* soc/intel/skylake: Drop unnecessary `ignore_vtd` optionAngel Pons2021-04-085-13/+3
* soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPDAngel Pons2021-04-084-5/+7
* soc/amd/picasso/acpi: fix domain argument of acpigen_write_CSD_packageFelix Held2021-04-071-1/+2
* soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge2021-04-072-0/+60
* vc/amd/fsp/cezanne: update UPD headersMatt Papageorge2021-04-072-2/+1
* intel/tigerlake: Add Acoustic featuresShaunak Saha2021-04-062-15/+10
* soc/intel/common: Prevent SMI storm when setting SPI WPD bitAngel Pons2021-04-064-0/+31
* soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake MMaulik V Vaghela2021-04-063-0/+5
* soc/intel/alderlake: Update variable SD3C to only track enabled devicesJohn Zhao2021-04-061-3/+7
* soc/intel/alderlake: Remove TCSS DMA _DSM methodJohn Zhao2021-04-061-5/+0
* soc/amd/cezanne: Add soc/msr.hRaul E Rangel2021-04-051-0/+24
* soc/amd/common: Add some ESPI register definitionsMartin Roth2021-04-051-5/+15
* soc/amd: Make espi_clear_decodes privateRaul E Rangel2021-04-053-11/+3
* soc/amd: Make espi_configure_decodes privateRaul E Rangel2021-04-055-18/+15
* soc/amd/common/espi: Clear DNCMD_COMPLETE on completionRaul E Rangel2021-04-051-0/+2
* soc/amd/common/espi: Reset eSPI registers to known stateRaul E Rangel2021-04-051-0/+8
* soc/amd/common/espi: Add missing eSPI register definitionsRaul E Rangel2021-04-051-0/+23
* device/dram/ddr3: Rename DDR3 SPD memory typesAngel Pons2021-04-051-6/+6
* device/dram/ddr3: Get rid of useless typedefsAngel Pons2021-04-051-1/+1
* soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_ENRaul E Rangel2021-04-051-4/+4
* soc/amd/cezanne: Clear eSPI ranges before configuring eSPIMartin Roth2021-04-051-0/+1
* soc/amd/common: Add func to clear eSPI IO & memory decode rangesMartin Roth2021-04-052-0/+28
* soc/ti/am335x/mmc.c: Fix memset length argumentAngel Pons2021-04-041-1/+1
* soc/amd/cezanne: Add support to perform early EC syncKarthikeyan Ramasubramanian2021-04-021-0/+4
* soc/amd/cezanne: Enable GENERIC_GPIO_LIBRaul E Rangel2021-04-011-0/+1
* soc/amd/cezanne: Add device tree support for I2CRaul E Rangel2021-04-011-0/+8
* soc/amd/common/block/graphics: Don't add VBIOS to cbmem when using GOPRaul E Rangel2021-03-311-1/+5
* soc/amd/picasso/acpi: pass correct enum to acpigen_write_CSD_packageFelix Held2021-03-311-1/+1
* soc/amd/cezanne: Comment the AOAC register accessKarthikeyan Ramasubramanian2021-03-301-6/+12
* soc/intel/alderlake: Enable logging of wake sources for S0ixSugnan Prabhu S2021-03-301-0/+2
* soc/intel/xeon_sp: Prepare for CBnT BPM generationArthur Heymans2021-03-302-2/+14
* soc/ti/am335x: Map useable RAMSam Lewis2021-03-301-0/+8
* soc/ti/am335x: Add SDRAM initialization driverSam Lewis2021-03-303-0/+714
* mb/ti/beaglebone: Load romstage/ramstage from SDSam Lewis2021-03-306-44/+26
* soc/ti/am335x: Add MMC/SD driverSam Lewis2021-03-302-0/+333
* soc/amd: smbus: Use correct type for uintptr_tPaul Menzel2021-03-291-2/+2
* soc/amd/cezanne: factor out UPD-M configuration from romstageFelix Held2021-03-293-17/+23
* soc/amd/picasso: factor out UPD-M configuration from romstageFelix Held2021-03-294-117/+122
* soc/amd/cezanne,picasso: rename fsp_params.c to fsp_s_params.cFelix Held2021-03-294-2/+2
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-30 14:22:17 +0000