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* soc/intel/tigerlake: Use PMC IPC to disable HECI1Subrata Banik2022-02-023-15/+4
| | | | | | | | | | | | | | | | | | | | This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Tiger Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/jasperlake: Use SBI msg to disable HECI1Subrata Banik2022-02-022-2/+2
| | | | | | | | | | | | | | Select HECI_DISABLE_USING_SMM config for Jasper Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/cannonlake: Use SBI msg to disable HECI1Subrata Banik2022-02-022-1/+2
| | | | | | | | | | | | | | Select HECI_DISABLE_USING_SMM config for Cannon Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6882b619506d1bf4131f68c2c9a32ef4f7d6f6d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/apollolake: Use PCR write to disable HECI1Subrata Banik2022-02-022-2/+3
| | | | | | | | | | | | | | Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Apollo Lake to disable HECI1 device using PCR writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8df9544296f0bea095c5415805a596cb5b36885e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/skylake: Use PCR write to disable HECI1Subrata Banik2022-02-022-2/+4
| | | | | | | | | | | | | | Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Skylake to disable HECI1 device using PCR writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/elkhartlake: Use SBI msg to disable HECI1Subrata Banik2022-02-021-0/+1
| | | | | | | | | | | | | | Select HECI_DISABLE_USING_SMM config for Elkhart Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4ef7ff7aa234ce411092d70bcb2c9141609be90e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/common/cse: Rework heci_disable functionSubrata Banik2022-02-0213-13/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH. Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure. Finally, rename heci_disable() function to heci1_disable() to make it more meaningful. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/intel/common/cse: Make cse_disable_mei_devices a public functionSubrata Banik2022-02-022-1/+4
| | | | | | | | | | | | | | | | | This patch export cse_disable_mei_devices() function instead of marking it static. Other IA common code may need to get access to this function for making `heci1` device disable. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* psp_verstage: report developer mode to PSPKangheui Won2022-02-014-0/+17
| | | | | | | | | | | | | | | | | | Add platform_report_mode function which report current developer mode status to the PSP. L1 widevine app in the PSP will use this information to select key box. BUG=b:211058864 TEST=build and boot guybrush TEST=build picasso chrome os boards Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* psp_verstage: add new svc for cezanneKangheui Won2022-02-011-0/+7
| | | | | | | | | | | | | | | Add svc_set_platform_bootmode svc to cezanne. PSP will use this information to select proper widevine keybox. BUG=b:211058864 TEST=build guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/samsung/exynos5420: Remove unuseful 'return' in void functionElyes HAOUAS2022-02-011-16/+0
| | | | | | | | Change-Id: I6c093e8326733a079ab3c41dfd2c77fe1883a9d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/nvidia/tegra124/sor.c: Remove unuseful 'return' in void functionElyes HAOUAS2022-02-011-2/+0
| | | | | | | | Change-Id: I8539eb9028f3141dfbeb926a1e19e3ad94be3edf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/nvidia/tegra210/sor.c: Remove unuseful 'return' in void functionElyes HAOUAS2022-02-011-2/+0
| | | | | | | | Change-Id: Ifaaf8a240436758a83216037994493255935f158 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/rockchip/rk3399/display.c: Remove unuseful 'return' in void functionElyes HAOUAS2022-02-011-2/+0
| | | | | | | | Change-Id: I8b5537bb6d0cb934aadb0eba8ba4f51dd53026c2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/qualcomm/ipq40xx/spi.c: Remove unuseful 'return' in void functionElyes HAOUAS2022-02-011-2/+0
| | | | | | | | Change-Id: I0ca7cbbf6c4884b58b4ec8a8e3cbc77f118a42f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/xeon_sp/acpi.c: Remove unuseful 'return' in void functionElyes HAOUAS2022-02-011-1/+0
| | | | | | | | Change-Id: Ib964939468ebb8cd0a537d514060ee5b8b13e320 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/samsung/exynos5250: Add missing 'void' in function definitionElyes HAOUAS2022-02-011-3/+3
| | | | | | | | Change-Id: I59203253ba9e66e4db3ff5dcae347b68d1203f21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* drivers/i2c/designware/dw_i2c: return enum cb_err from dw_i2c_initFelix Held2022-02-012-2/+2
| | | | | | | | | | | | Using enum cb_err as return type instead of int improves the readability of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* soc/intel/common: Add the Primary to Sideband bridge libraryJohn Zhao2022-02-015-44/+126
| | | | | | | | | | | | | | | | | New platforms have additional Primary to Sideband bridge besides the PCH P2SB. This change puts the common functions into the P2SB library. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/appololake: Allow to configure SATA ALPM via devicetreeMario Scheithauer2022-02-012-0/+7
| | | | | | | | | | | | | | | Add a devicetree option to disable SATA Aggressive Link Power Management. ALPM is a method of saving power. The corresponding FSP-S UPD parameter is enabled by default. It may be that this feature is unwanted, for example for a real-time system. Therefore, allow to disable ALPM using the devicetree. Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/alderlake: Add PMC register base for ADL-NUsha P2022-02-011-0/+5
| | | | | | | | | | | | | Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated from the FSP code. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61148 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_SCS for Alder Lake NKrishna Prasad Bhat2022-02-012-0/+3
| | | | | | | | | | | | Alder Lake N has eMMC storage device. Select SOC_INTEL_COMMON_BLOCK_SCS Kconfig for Alder Lake N. Change-Id: I577ffdc80ef09471309c827551a347d4397a33d1 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake NKrishna Prasad Bhat2022-02-011-0/+3
| | | | | | | | | | | | Alder Lake N has eMMC storage device. Add PCR Port ID for it. Reference: Alder Lake N platform EDS Doc# 645548. Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOCKrishna Prasad Bhat2022-02-014-49/+301
| | | | | | | | | | | | | | | | | | | | | Add definitions for GPP_I GPIO group pins on Alder Lake N SOC and GPIO IRQ routing information. GPP_I GPIO group belongs to GPIO community 1. Hence GPIO community 1 in Alder Lake N contains GPP_S, GPP_I, GPP_H, GPP_D GPIO groups. GPIO groups 1-6 in Doc# 645550 Chapter 36 corresponds to GPIO communities 5-0 respectively. BUG=b:213535859 Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61106 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/adl: Update devicetree based on remapping for TBT PCIeMAULIK V VAGHELA2022-01-314-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe coalescing logic where in case root port 0 is disabled, other enabled root port is remapped to port 0. coreboot handles this remapping scenarios for PCH and CPU PCIe root ports and not for TBT root ports. This patch uses the same function used for PCIe remapping to update devicetree based on coalescing and SoC needs to pass correct function number and number of slots. BUG=b:210933428 BRANCH=None TEST=Check if TBT remapping happens correctly and ACPI tables are generated correctly. Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtreeMAULIK V VAGHELA2022-01-311-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | pcie_rp_update_devicetree function takes pcie_rp_group strcuture as an argument and SoC code passes the parameter in this structure. This pointer can be NULL and common code may try to dereference this NULL pointer. Also, group might have no data and SoC may pass this by indicating group count as zero (For example, for CPU or TBT root ports). These checks will prevent function from executing redundant code and returning early from the call as it's not required. BUG=b:210933428 BRANCH=None TEST=check if function returns early for group count 0 and there is no issue while booting board in case group count = 0. Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/amd/sabrina: Add PRE_X86_CBMEM_CONSOLE_SIZEFelix Held2022-01-311-0/+6
| | | | | | | | | | | | | | Commit 86302a806c5cc9b575424305e761753710417692 (soc/amd/{common, cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE) added this Kconfig option before the initial commit that added soc/amd/sabrina as copy of soc/amd/cezanne landed in the tree, so port the change forward to Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2e8df5e7b7f1ac0af772e8c565f616a68b28e29e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/intel/alderlake: Add Alder Lake P IGD device IDsKane Chen2022-01-312-0/+6
| | | | | | | | | | | | | | This patch adds additional IGD device IDs as per document 638514. BUG=b:216420554 TEST=coreboot is able to probe the IGD device during PCI enumeration. Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Drop stale eNEM TODO commentSubrata Banik2022-01-301-1/+1
| | | | | | | | | | | | | | | This patch drops stale TODO comment about enabling eNEM on EHL. eNEM is non-POR on the elkhartlake product. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/mediatek/mt8186: Add register protect control for MT6366Rex-BC Chen2022-01-291-5/+12
| | | | | | | | | | | | | | | Some registers of PMIC init settings are protected, so we failed to set the correct value for init_setting. We disable protection before setting PMIC init setting and enable it afterward. BUG=b:216263707 TEST=PMIC setting value is set correctly. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I94d73d9c8a137444988e65c3709d29a3a4c03c5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61390 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sc7280: Add Modem region to avoid modem cleanup in Secboot rebootT Michael Turney2022-01-285-0/+31
| | | | | | | | | | | | | | Modem uses different memory regions based on LTE/WiFi. This adds correct carve-out to prevent region being disturbed. BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: T Michael Turney <quic_mturney@quicinc.com> Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* soc/intel/xeon_sp/nb_acpi.c: Drop comparison to trueElyes HAOUAS2022-01-281-1/+1
| | | | | | | | Change-Id: Ib9670ee22e36dd988a75b2f8dc565534927b6107 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* sc7280: enable bl31 and SDI feature supportRavi Kumar Bokka2022-01-282-0/+21
| | | | | | | | | | | BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I61c695fb4fef3ae36ffc5a263236b9d40c299dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* soc/intel/common/gpio: Skip GPIO PAD locking in recovery modeSubrata Banik2022-01-281-2/+3
| | | | | | | | | | | | | | | The recovery mode is meant to provide fixes for the platform deformity hence, skip locking the GPIO PAD configuration to provide the same flexibility to the platform owner while booting in recovery mode. BUG=b:211950520 TEST=Able to build and boot the brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0f0a3cfb2be7f2a5485679f6a3d8cb4fb407fcf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/intel: Abstract the common block API for TCSS registers accessJohn Zhao2022-01-287-11/+49
| | | | | | | | | | | | | | | | The existing TCSS registers access is through the REGBAR. There will be future platforms which access the TCSS registers through the Sideband interface. This change abstracts the common block API for TCSS access. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3e2696b117af24412d73b257f470efc40caa5022 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* src/{drivers,soc}: Fix some code indentsElyes HAOUAS2022-01-284-9/+9
| | | | | | | | | Change-Id: I55682de4a1bc74f170e2044de35b0d8d53ef51ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/common/cse: skip heci_init() if HECI1 is disabledMatt DeVillier2022-01-281-0/+4
| | | | | | | | | | | | | | | | | If the HECI1 PCI device is disabled, either via devicetree or other method (HAP, me_cleaner), then we don't want/need to program a BAR, set the PCI config, or call heci_reset(), as the latter will result in a 15s timeout delay when booting. Test: build/boot Purism Librem 13v2, verify heci_reset() timeout delay is no longer present. Change-Id: I0babe417173d10e37327538dc9e7aae980225367 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: Enable CPPCv3Sridahr Siricilla2022-01-282-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | The patch defines the following helper functions: get_cpu_scaling_factor(): Returns scaling factors of big and small core. cpu_is_nominal_freq_supported(): Returns true if CPU supports Nominal Frequency, otherwise false. cpu_is_nominal_freq_supported(): Check CPU supports nominal frequency or not. The patch also enables CPPCv3 support for Intel Alder Lake which is based on hybrid core architecture. TEST=Verified Nominal Frequency and Nominal Performance are getting updated for ADL-P small and big cores correctly. Signed-off-by: Sridahr Siricilla <sridhar.siricilla@intel.com> Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Implement ACPI CPPCv3 package to support hybrid coreSridhar Siricilla2022-01-283-2/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch implements ACPI CPPCv3 package. It implements and updates the following methods: generate_cppc_entries(): Updates method to support CPPCv3 package acpi_get_cpu_nominal_freq(): Calculates CPU's nominal frequency acpi_get_cpu_nomi_perf(): Calculates nominal performance for big and small cores. acpigen_write_CPPC_hybrid_method(): It generates ACPI code to implement _CPC method. acpigen_cppc_update_nominal_freq_perf(): It updates CPPC3 package if cpu supports Nominal Frequency. It generates ACPI code which sets Nominal Frequency and updates Nominal Performance. It uses below calculation to update the Nominal Frequency and Nominal Performance: Nominal Frequency = Max non-turbo ratio * cpu_bus_frequency Nominal Performance = Max non-turn ratio * cpu scaling factor CPU scaling factor varies in the hybrid core environment. So, the generated ACPI code updates Nominal Performance based on the CPU's scaling factor. TEST=Verified CPPCv3 package is getting created in the SSDT table. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: ravindr1 <ravindra@intel.com> Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* soc/amd/sabrina/chipset.cb: update USB portsFelix Held2022-01-271-19/+5
| | | | | | | | | | | The corresponding mainboard design guide was used as a reference here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina/include/smu: update mailbox SMN addressesFelix Held2022-01-272-5/+1
| | | | | | | | | | | The SMU message response register was moved compared to Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie384de52b1efb1d52f9018315a4b72916a4c9cee Reviewed-on: https://review.coreboot.org/c/coreboot/+/61095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina/include/southbridge: add new I2C_PAD_CTRL bitsFelix Held2022-01-271-0/+3
| | | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac1b7308851c34bd1556c02af6b270e9346073e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina: drop PM_ESPI_CS_USE_DATA2 define and eSPI util codeFelix Held2022-01-274-48/+0
| | | | | | | | | | | | | | | The Sabrina SoC doesn't have the PM_ESPI_CS_USE_DATA2 bit defined in the PM_SPI_PAD_PU_PD register. It also doesn't have a physical LPC interface any more, so there are no LPC pins that can be reconfigured as eSPI interface. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I02bc8d007901c71942475fe707637c5da7227230 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina: drop CPPC codeFelix Held2022-01-277-114/+0
| | | | | | | | | | | The CPPC feature isn't available on the Sabrina SoC, so drop the corresponding code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71a1b0717571729ebca3600ac433e621cafc4e61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina: update PCI devices in devicetree.cbFelix Held2022-01-271-12/+2
| | | | | | | | | | Also update mb/amd/chausie accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb4dcffa48c3dbdcffb66f1398b99ee96562efb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina: update pci_devs.hFelix Held2022-01-271-28/+2
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic0226afd9e7fffd6bf196f06ee6c34b6b9c92f30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina/fsp_m_params: drop sata_enable UPD writeFelix Held2022-01-271-1/+0
| | | | | | | | | | | | There are no SATA controllers on the Sabrina SoC. The UPD field will be removed later as a part of the initial UPD header update. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iedefd9f150e5bcb78173288e5fc9f1bbd6b498cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/sabrina/include: update smi.hFelix Held2022-01-271-17/+22
| | | | | | | | | | | | Some of the names have slightly changed in the PPR, but I kept the current names for consistency across all AMD SoCs in coreboot. Revision 1.50 of the PPR #57243 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6bda656015858a57e221b8d7819f944c21564a39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina/include/data_fabric: update IOMS0_FABRIC_IDFelix Held2022-01-271-3/+1
| | | | | | | | | | | | The data fabric ID table in PPR #57243 Rev 1.50 has a different IOMS0 fabric ID than Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32890b5c03219f6ebf8180929d71ef726d382483 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/sabrina: drop graphics.cFelix Held2022-01-273-27/+0
| | | | | | | | | | | Since we don't need to support PCI ID remapping for finding the correct VBIOS binary for the integrated GPU, graphics.c can be dropped for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd5b678f472b3b5888353efd057203eb641be874 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 18:57:21 +0000