summaryrefslogtreecommitdiffstats
path: root/src/soc
Commit message (Expand)AuthorAgeFilesLines
* t132: add Kconfig option for MTS microcode directoryAaron Durbin2015-03-072-1/+15
* tegra132: add preboot MTS to bct generationAaron Durbin2015-03-071-2/+6
* tegra132: add support for TZ carve-outAaron Durbin2015-03-054-1/+53
* t132: handle carve-outs for addressable memoryAaron Durbin2015-03-053-9/+129
* t132: Enable cbmem console supportAaron Durbin2015-03-058-30/+76
* t132: bring up 64-bit denver coreAaron Durbin2015-03-057-7/+231
* fsp_baytrail: Add I2C driverWerner Zeh2015-03-053-0/+396
* fsp_baytrail: Add new microcode for Bay Trail MWerner Zeh2015-03-053-9/+21
* coreboot t132: Stack init re-workFurquan Shaikh2015-03-046-39/+112
* t132: kick off core complex after loading MTS microcodeAaron Durbin2015-03-041-1/+47
* t132: load MTS microcodeAaron Durbin2015-03-044-2/+95
* t132: Replace fallback with CONFIG_CBFS_PREFIXMarc Jones2015-03-042-2/+4
* t132: Add shared romstageAaron Durbin2015-03-043-0/+74
* coreboot rush: Add dram init codeFurquan Shaikh2015-03-048-0/+2590
* coreboot rush: Add support for basic romstageFurquan Shaikh2015-03-041-1/+2
* coreboot t132: Enable loading of romstage from CBFS mediaFurquan Shaikh2015-03-043-2/+26
* coreboot t132: Remove init pllx for nowFurquan Shaikh2015-03-042-8/+5
* coreboot t132,rush: Add mainboard specific bootblock_initFurquan Shaikh2015-03-049-0/+1517
* coreboot t132: Add clock.c to all three stages of corebootFurquan Shaikh2015-03-033-53/+6
* coreboot arm: Define function for setting cntfrq registerFurquan Shaikh2015-03-022-37/+50
* tegra132: Enable bootblock support in tegra132 including UART supportFurquan Shaikh2015-03-0215-8/+2501
* x86: Fix pointer arithmetic regressions from MMIO changesKevin Paul Herbert2015-02-271-2/+2
* tegra124: Clean up ARM UART driver buildMarc Jones2015-02-251-4/+4
* soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`Paul Menzel2015-02-251-1/+0
* intel/broadwell: free local heap objectPatrick Georgi2015-02-251-0/+1
* soc/fsp_baytrail: Fix use of microcode-related Kconfig variablesAlexandru Gagniuc2015-02-242-11/+9
* tegra132: Postprocess bootblock properlyPatrick Georgi2015-02-171-2/+2
* tegra132: Add BCT support in tegra132 socFurquan Shaikh2015-02-172-2/+31
* T124: perform ram_repair when CPU rail is powered on in warmbootYen Lin2015-02-171-0/+29
* T124: perform ram_repair when CPU rail is powered on in coldbootYen Lin2015-02-174-1/+35
* tegra124: Correct cpu power on sequence and CPUPWRGOOD_TIMEJimmy Zhang2015-02-175-28/+41
* acpi: Generate valid ACPI processor objectsTimothy Pearson2015-02-165-107/+107
* x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert2015-02-1536-202/+213
* tegra132: Fix build for verstageMarc Jones2015-02-131-0/+1
* fsp_baytrail: Add macros to define 20K pull-up and downWerner Zeh2015-02-131-0/+14
* Baytrail_fsp: Make ME path configurable in menuconfigWerner Zeh2015-02-101-1/+1
* fsp_baytrail: Get FSP reserved memory from the FSP HOB listMartin Roth2015-02-093-16/+8
* Intel FSP platforms: Fix timestampsKyösti Mälkki2015-02-091-5/+6
* include/types.h: Provide BIT() macroAlexandru Gagniuc2015-02-063-2/+1
* FSP & CBMEM: Fix broken cbmem CAR transition.Martin Roth2015-02-062-1/+2
* CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki2015-01-277-8/+0
* CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki2015-01-277-61/+35
* CBMEM: Move cbmemc_reinit()Kyösti Mälkki2015-01-271-1/+0
* vboot2: implement select_firmware for pre-romstage verificationDaisuke Nojiri2015-01-273-1/+26
* vboot2: add verstageStefan Reinauer2015-01-2712-2/+26
* tegra132: Add support for tegra132 socFurquan Shaikh2015-01-2611-0/+713
* baytrail: there is a chance that USBPHY_COMPBG is set to 0Kane Chen2015-01-161-1/+3
* baytrail: use the setting in devicetree.cb to config USBPHY_COMPBGKane Chen2015-01-162-1/+3
* baytrail broadwell: Use timestamps internal stashKyösti Mälkki2015-01-144-50/+10
* Revert "vboot2: add verstage"Paul Menzel2015-01-145-22/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 13:21:43 +0000