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* soc/intel/alderlake: remove duplicate PL2 overrideSumeet R Pawnikar2021-05-041-2/+0
* soc/intel/*: Update data types for variables holding PCH_DEVFN_* macrosTim Wawrzynczak2021-05-034-4/+4
* device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak2021-05-033-51/+20
* soc/amd/picasso/dmi.c: Fix builds for boards without Google ECNikolai Vyssotski2021-05-031-1/+1
* soc/intel/alderlake: Enable HWP CPPC support in CBravindr12021-05-031-0/+1
* soc/intel/alderlake: Fill FSPM UPDs for VT-d configurationMeera Ravindranath2021-05-031-3/+30
* soc/intel/cannonlake/include: Drop unused codeFelix Singer2021-05-021-9/+0
* soc/intel/skylake: Remove useless help textsFelix Singer2021-05-021-6/+0
* soc/intel/cannonlake: Remove useless help textsFelix Singer2021-05-021-8/+0
* soc/amd/cezanne: add verstage filesKangheui Won2021-05-027-2/+264
* soc/intel/skylake: Add Kconfig option for LGA1151v2Timofey Komarov2021-05-011-4/+26
* soc/intel/skylake: Add microcodes for Coffee Lake CPUsTimofey Komarov2021-05-012-0/+10
* soc/amd/common: Move external oscillator config away from commonKarthikeyan Ramasubramanian2021-04-303-6/+5
* amd/cezanne: Add telemetry setting to UPDChris Wang2021-04-302-0/+17
* soc/mediatek/mt8192: devapc: Add ADSP domain settingTinghan Shen2021-04-302-2/+4
* soc/amd/common: Remove eSPI decode workaroundRaul E Rangel2021-04-291-5/+1
* psp_verstage: make temp_stack optionalKangheui Won2021-04-291-0/+2
* psp_verstage: make get_max_workbuf_size optionalKangheui Won2021-04-293-3/+18
* soc/amd/picasso: move PSP_SRAM addrs to separate headerKangheui Won2021-04-292-27/+32
* soc/amd/cezanne: Enable Audio Co-processor driverKarthikeyan Ramasubramanian2021-04-291-0/+1
* soc/amd/common/acp: Move Audio Co-processor driver to commonKarthikeyan Ramasubramanian2021-04-2910-46/+54
* soc/intel/common/block/hda: Use azalia device codePatrick Rudolph2021-04-282-39/+6
* soc/amd/common/smi_handler: Print warning when receiving an SCI SMIRaul E Rangel2021-04-281-1/+5
* soc/amd/cezanne: copy psp_transfer.h from picassoKangheui Won2021-04-281-0/+49
* soc/amd/cezanne: copy Kconfig options for psp_verstageKangheui Won2021-04-281-1/+72
* soc/intel: Add Z370, H310C and B365 device IDsAngel Pons2021-04-282-0/+6
* soc/intel: Add Kaby Lake PCH-U base device IDAngel Pons2021-04-282-0/+2
* soc/intel/skylake: Shorten report_platform PCH-H namesAngel Pons2021-04-281-19/+19
* soc/intel: Rename 200-series PCH device IDsAngel Pons2021-04-287-49/+49
* soc/intel/skylake: Drop Lewisburg PCHs from report_platformAngel Pons2021-04-281-13/+0
* soc/mediatek/mt8195: Add PLL and clock init supportWeiyi Lu2021-04-286-0/+1876
* soc/mediatek: Move the common part of PMIC drivers to common/Yidi Lin2021-04-2821-1053/+1100
* soc/amd/cezanne: Update STAPM vars with unitsMartin Roth2021-04-262-8/+8
* amd/cezanne: Add slow_ppt_time & thermctl_limit to UPDMartin Roth2021-04-262-0/+4
* haswell/broadwell: Replace remaining MCHBAR accessorsAngel Pons2021-04-266-40/+33
* soc/intel/elkhartlake: Remove elog.cTan, Lean Sheng2021-04-262-118/+0
* soc/intel/elkhartlake: Update GPIO communitiesTan, Lean Sheng2021-04-266-555/+757
* src/soc/amd/picasso: Add HDMI 2.0 disable settingPatrick Huang2021-04-262-0/+7
* soc/amd/cezanne/fsp_m_params: Configure the s0i3_enable UPDKarthikeyan Ramasubramanian2021-04-261-0/+3
* soc/intel/alderlake: Use device ID from pci_devs header fileJohn Zhao2021-04-261-4/+5
* soc/intel/alderlake: Fix devices list in the DMAR DRHD structureJohn Zhao2021-04-261-17/+17
* soc/intel/tigerlake: Use device ID from pci_devs header fileJohn Zhao2021-04-261-4/+5
* soc/amd/cezanne,picasso/Kconfig: add help text for MAX_CPUSFelix Held2021-04-262-0/+4
* soc/mediatek/mt8195: Add GPIO driverPo Xu2021-04-264-0/+613
* soc/mediatek/mt8195: Add timer supportYidi Lin2021-04-2612-48/+158
* soc/mediatek/mt8192: Remove redundant SPM register definitionYidi Lin2021-04-263-10/+4
* soc/mediatek/mt8195: add register definitionsYidi Lin2021-04-263-0/+1445
* soc/mediatek/mt8195: Initialize watchdogYidi Lin2021-04-266-1/+18
* soc/amd/cezanne & picasso: Add Kconfig for hardcoded Soft Fuse bitsMartin Roth2021-04-264-5/+33
* Coachz: Observe SPI_CLK voltage level is only 1.4V, need to adjustyolkshih2021-04-241-1/+1
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