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* build system: Structure and serialize INTERMEDIATEPatrick Georgi2021-01-142-7/+2
* soc/amd/picasso/uart: add missing device/device.h includeFelix Held2021-01-141-0/+1
* soc/amd/cezanne: add remaining non-ACPI parts of UART supportFelix Held2021-01-141-0/+35
* soc/amd/cezanne: add AOAC supportFelix Held2021-01-145-1/+77
* soc/amd/cezanne: add console UART supportFelix Held2021-01-147-0/+87
* soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UARTFelix Held2021-01-144-27/+10
* soc/amd/common/block/uart/Makefile: use all targetFelix Held2021-01-141-7/+1
* soc/amd/piasso/uart: move get_uart_base prototype to common code headerFelix Held2021-01-144-3/+12
* soc/amd/common/uart: move CONSOLE_UART_BASE_ADDRESS back to SoC codeFelix Held2021-01-142-14/+8
* soc/amd/picasso: remove broken and unused legacy UART supportFelix Held2021-01-144-99/+1
* soc/amd/picasso: Disable CBFS MCACHERaul E Rangel2021-01-131-0/+1
* ACPI: Have single call-site for acpi_inject_nvsa()Kyösti Mälkki2021-01-1314-48/+0
* ACPI: Add common acpi_fill_gnvs()Kyösti Mälkki2021-01-138-50/+0
* soc/amd: Rename to soc_fill_gnvs()Kyösti Mälkki2021-01-132-26/+12
* soc/amd: Rename to pm_fill_gnvs()Kyösti Mälkki2021-01-134-13/+9
* soc/intel/tigerlake: Disable TC cold supportSrinidhi N Kaushik2021-01-131-0/+3
* soc/intel: rename uart_max_indexMichael Niewöhner2021-01-129-10/+10
* soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE`Angel Pons2021-01-122-2/+1
* soc/intel/common/pcie: Add helper function for getting mask of enabled portsFurquan Shaikh2021-01-123-0/+58
* soc/intel/alderlake: Add PCH ID 0x5182Subrata Banik2021-01-122-1/+3
* soc/intel/{icl,tgl,jsl,ehl}: add LPIT supportMichael Niewöhner2021-01-118-0/+12
* soc/intel/skl: add SLP_S0 residency register and enable LPIT supportMichael Niewöhner2021-01-112-0/+2
* soc/intel/cnl: add SLP_S0 residency register and enable LPIT supportMichael Niewöhner2021-01-112-0/+3
* acpi,soc/intel/common: add support for Intel Low Power Idle TableMichael Niewöhner2021-01-114-0/+74
* {soc,vc,mb}/intel: Drop support for Cannon Lake SoCFelix Singer2021-01-114-34/+0
* soc/amd/cezzane: Add a minimal chipset treeFurquan Shaikh2021-01-112-0/+9
* soc/intel/common/uart: Use simple(_s_) variants of PCI functionsFurquan Shaikh2021-01-111-41/+34
* soc/intel/uart: Drop SoC callback `soc_uart_console_to_device`Furquan Shaikh2021-01-1110-194/+49
* soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-SJeremy Soller2021-01-111-0/+47
* soc/amd/picasso: Separate GPIO define into gpio_defs.hEric Lai2021-01-113-244/+250
* soc/intel/cannonlake: Enable wake from USB in S4Patrick Rudolph2021-01-111-1/+4
* soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPsSubrata Banik2021-01-104-14/+28
* soc/intel/broadwell: Use `mp_cpu_bus_init`Angel Pons2021-01-103-5/+2
* mb/google/cyan: Move board_id() to mainboard_fill_gnvs()Kyösti Mälkki2021-01-101-12/+0
* ACPI: Add missing include in nvs.hKyösti Mälkki2021-01-106-0/+6
* soc/intel: Rename to soc_fill_gnvs()Kyösti Mälkki2021-01-1010-15/+13
* soc/intel: Replace acpi_init_gnvs()Kyösti Mälkki2021-01-105-4/+7
* mb/x/acpi_tables: Rename to mainboard_fill_gnvs()Kyösti Mälkki2021-01-104-4/+5
* sb/intel: Factor out soc_fill_gnvs()Kyösti Mälkki2021-01-101-5/+9
* ACPI: Replace uses of CBMEM_ID_ACPI_GNVSKyösti Mälkki2021-01-106-71/+34
* soc/intel/braswell: Refactor acpi_init_gnvs()Kyösti Mälkki2021-01-101-6/+6
* ACPI: Drop redundant ChromeOS setup for GNVSKyösti Mälkki2021-01-1013-140/+0
* ACPI: Drop redundant CONSOLE_CBMEM setup in GNVSKyösti Mälkki2021-01-1015-65/+0
* ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocationsKyösti Mälkki2021-01-1019-87/+26
* soc/amd/picasso: add missing GNB I/O APIC initializationFelix Held2021-01-081-0/+7
* soc/intel/common/uart: Restrict scope of uart_common_init to uart.cFurquan Shaikh2021-01-082-7/+1
* soc/intel/common: Pass in pci_devfn_t into lpss_set_power_stateFurquan Shaikh2021-01-085-26/+10
* soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range()Furquan Shaikh2021-01-0810-25/+18
* soc/intel/tigerlake: Enable USB2 port reset message on Type-C portsJohn Zhao2021-01-082-0/+5
* soc/amd/picasso: Generate GNB IO-APIC PCI routing tableRaul E Rangel2021-01-081-30/+100
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