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* soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the topFelix Held2021-11-053-3/+6
| | | | | | | | | | | | Since all other defines for the number of certain things are at the top of the file, move NUMBER_SMITYPES there as well to keep things consistent. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/*/include/smi: fix off-by-one in SCIMAPS definesFelix Held2021-11-053-3/+3
| | | | | | | | | | | | | SCIMAPS is the total number of SCI to GEVENT mappings. configure_scimap returns early when the scimap is greater or equal than SCIMAPS, so for SMITYPE_ACDC_TIMER it returned early without doing what was expected from it to do despite that being a valid value, so fix this off-by-one. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf8c5618ddbf0b8d4cd612a7f1347d8562bbfcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/mediatek/mt8186: Enable and initialize EINTRex-BC Chen2021-11-052-0/+3
| | | | | | | | | | | | | | | | | EINT event mask register is used to mask EINT wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel EINT upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I84946c2c74dd233419cb94f013a42c734363baf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add timer supportRex-BC Chen2021-11-052-4/+20
| | | | | | | | | | | | | Add timer drivers to use timer function. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6524e4dec4cbe7f7eb75a7940c329416559a03c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add PLL and clock init supportChun-Jie Chen2021-11-056-0/+2527
| | | | | | | | | | | | | | Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: Id46d0708e7ba0c1a4043a5dce33ef69421cb59c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folderRex-BC Chen2021-11-052-0/+47
| | | | | | | | | | | | | | | The NOR-Flash can be configured on SPI0 or TDM-RX GPIOs so we have to provide an init function in SoC for the mainboard to select right configuration. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I285ec64ace8b72a48ef1d481d366bd67cb9b0337 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/intel/denverton_ns: Refactor `detect_num_cpus_via_cpuid()`Angel Pons2021-11-051-11/+10
| | | | | | | | | | | Rewrite level type check and use unsigned types. In addition, also use unsigned types in the `get_cpu_count()` function. Change-Id: I63f236f0f94f9412ec03ae25781befe619cf7c1f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/xeon_sp: Refactor `get_threads_per_package()`Angel Pons2021-11-052-2/+1
| | | | | | | | | | | Reduce the visibility of the `get_threads_per_package()` function and retype its return value to `unsigned int`. Change-Id: Ie71730d9a89eb7c4bb82d09d140fbcec7a6fe5f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/braswell: Make `num_cpus` unsignedAngel Pons2021-11-051-1/+1
| | | | | | | | Change-Id: Iff6da3dc9c744a3dae3f4dd4ac37a91f348450a3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/baytrail: Make `num_cpus` unsignedAngel Pons2021-11-051-1/+1
| | | | | | | | Change-Id: I9ab0106c27a834d5d2ac1cb8023f4400a8ad91cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel: Replace bad uses of `find_resource`Angel Pons2021-11-0422-32/+32
| | | | | | | | | | | | | | The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I2a57ea1c2f5b156afd0724829e5b1880246f351f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/common/block/spi: Add prompt to SOC_AMD_COMMON_BLOCK_SPI_DEBUGRaul E Rangel2021-11-041-1/+1
| | | | | | | | | | | | | Makes it so I can enable SPI debugging without modifying the source. BUG=b:179699789 TEST=Add CONFIG_SOC_AMD_COMMON_BLOCK_SPI_DEBUG=y to my .config Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie3815e0398b5268874039196a625fc29dd3dc3d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Kconfig,soc/amd/cezanne: Make COOP_MULTITASKING select TIMER_QUEUERaul E Rangel2021-11-041-1/+0
| | | | | | | | | | | | | This reduces the number of selects required in the SOC_SPECIFIC_OPTIONS. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f1364fc269ea5ec17982bf750a164a3290adb0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMARaul E Rangel2021-11-041-0/+6
| | | | | | | | | | | | | | | | AMD platforms require the destination buffer to be 64 byte aligned when using the SPI DMA controller. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* amd/i2c: Remove the weak functionZheng Bao2021-11-042-5/+6
| | | | | | | | | | BUG=b:140165023 Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/cezanne/include/gpio: fix GPIO 106 native function namesFelix Held2021-11-041-2/+2
| | | | | | | | | | | The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed that the native function names don't have the EMMC_ prefix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guardFelix Held2021-11-041-3/+3
| | | | | | | | | | This makes this header file consistent with the rest. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/mediatek/mt8186: Add NOR-Flash supportRex-BC Chen2021-11-044-0/+25
| | | | | | | | | | | | | | Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If51d765e1fd4895f97898710ec6fa1374e1048fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58837 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Add GPIO driversGuodong Liu2021-11-034-0/+751
| | | | | | | | | | | | | | Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/58836 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Initialize watchdogRex-BC Chen2021-11-034-0/+24
| | | | | | | | | | | | | | | | MT8186 requires writing speical value to mode register to clear status register. The flow of clear status is different from other platforms, so we override mtk_wdt_clr_status() for MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58835 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Add an overridable function for WDT clear statusRex-BC Chen2021-11-036-13/+20
| | | | | | | | | | | | | | | mtk_wdt_clr_status is different for MT8186 and MT8195, so we move this function to soc folder. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne/include/aoac_defs: drop leading newlineFelix Held2021-11-031-1/+0
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8458fbee7edd19117a207f39ac8f9575b1374fbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guardsFelix Held2021-11-032-6/+6
| | | | | | | | | | | Somehow missed renaming those when creating the coreboot support for Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/*/cpu: handle mp_init_with_smm failureFelix Held2021-11-033-9/+9
| | | | | | | | | | | | | | | | | | | When the mp_init_with_smm call returns a failure, coreboot can't just continue with the initialization and boot process due to the system being in a bad state. Ignoring the failure here would just cause the boot process failing elsewhere where it may not be obvious that the failed multi-processor initialization step was the root cause of that. I'm not 100% sure if calling do_cold_reset or calling die_with_post_code is the better option here. Calling do_cold_reset likely here would likely result in a boot-failure loop, so I call die_with_post_code here. BUG=b:193809448 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* cpu/amd/mtrr: Remove topmem global variablesArthur Heymans2021-11-032-2/+1
| | | | | | | | | | | | The comments are not correct anymore. With AGESA there is no need to synchronize TOM_MEMx msr's between AP's. It's also not the best place to do so anyway. Change-Id: Iecbe1553035680b7c3780338070b852606d74d15 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cpu/x86/Kconfig: Remove unused CPU_ADDR_BITSArthur Heymans2021-11-036-24/+0
| | | | | | | | | Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
* soc/amd/stoneyridge/cpu: remove unneeded line break in get_cpu_countFelix Held2021-11-031-2/+1
| | | | | | | | | | | The line length is no longer limited to 80 characters, so there's no need for that line break any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7a8fb472f00e039f25a71ee526a3dd0bc6c754f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/xeon_sp: disable PM ACPI timer if chosenMichael Niewöhner2021-11-033-0/+17
| | | | | | | | | | | | | | | | Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is disabled. This is done to bring SKL, CNL, DNV in line with the other platforms, in order to transition handling of the PM timer from FSP to coreboot in the follow-up changes. Disabling is done in `finalize` since FSP makes use of the PMtimer. Without PM Timer emulation disabling it too early would block. Change-Id: If85c64ba578991a1b112ceac7dd10276b58b0900 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
* soc/intel/alderlake: Allow devicetree override to leave some VR settings as ↵Bora Guvendik2021-11-031-3/+6
| | | | | | | | | | | | | | default Allow devicetree override to leave ac_loadline, dc_loadline and icc_max as default. Test=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I715345d5ea83aed9ee929b2a4e13921c9d8895b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoCRex-BC Chen2021-11-0312-0/+318
| | | | | | | | | | | | | | | | | | | | Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: move timer enum variables to timer_v2.hRex-BC Chen2021-11-032-12/+13
| | | | | | | | | | | | | | | Some enum variables of timer v2 are the same between MT8195 and MT8186, so we move them to common timer_v2.h. TEST=emerge-cherry coreboot BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58829 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: add apusys init flowFlora Fu2021-11-035-0/+66
| | | | | | | | | | | | | | Set up APU mbox's functional configuration registers. BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58794 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/denverton_ns: Fetch addr bits at runtimeArthur Heymans2021-11-021-1/+2
| | | | | | | | | Change-Id: Ic46a7d56cbaf45724ebc2a1911f5096af2fe461a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDsFelix Held2021-11-022-1/+3
| | | | | | | | | | | | | | | | PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS redefine the same values that are already defined by PCI_DEVICE_ID_AMD_CZ_LPC and PCI_DEVICE_ID_AMD_CZ_SMBUS, so drop PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS. Also add some comments to the places in the code where the defines are used to clarify which ID is used on which hardware generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/58696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/cpu: Add support for cbfs_cache regionRaul E Rangel2021-11-022-0/+14
| | | | | | | | | | | | | | | This change adds the cbfs_cache region into the x86 memlayout. The SoC or mainboard can decide how big the region should be by specifying CBFS_CACHE_SIZE. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache region wasn't added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* psp_verstage: convert relative address in EFS2Kangheui Won2021-11-024-4/+13
| | | | | | | | | | | | | | | | | Addresses in AMD fw table with EFS gen2 are relative addresses, but PSP doesn't accept relative addresses in update_psp_bios_dir(). Check for EFS gen2 and convert them as needed. BUG=b:194263115 TEST=build and boot on guybrush and shuboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I95813beba7278480e6640599fcf7445923259361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()Subrata Banik2021-11-023-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* soc/intel: Don't send CSE EOP if CSME is disabledSean Rhodes2021-11-011-0/+12
| | | | | | | | | | CSE EOP will fail if the CSE is disabled (CB:52800) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic00fdb0d97fefac977c0878d1d5893d07d4481ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/57149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/braswell: Set GNVS DPTE via devicetreeAngel Pons2021-11-012-0/+8
| | | | | | | | | | | | Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS field, as newer Intel platforms do. Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* soc/intel/braswell/chip.h: Use `bool` typeAngel Pons2021-11-011-8/+8
| | | | | | | | | | | Use `bool` type where applicable. Change-Id: I4d5422c16381676738b8614e8e50737b59739921 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* amd/lpc: Remove the weak functionZheng Bao2021-11-012-7/+0
| | | | | | | | | | BUG=b:140165023 Change-Id: Idb4613dc08c8dee6c92b4dabb39c2f5c189471aa Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/common/block/cse: Add get_me_fw_version functionJohnny Lin2021-11-012-30/+48
| | | | | | | | | | | | | | | Modify print_me_fw_version to get ME firmware version by calling it. Tested=On a not yet to be public platform, verified the function can get ME FW version successfully. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I50d472a413bcaaaa085955657bde6a0e6ec2c1db Reviewed-on: https://review.coreboot.org/c/coreboot/+/58520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* lib: Use `smbios_bus_width_to_spd_width` for setting dimm.bus_widthSubrata Banik2021-10-301-21/+8
| | | | | | | | | | | | | | | Make use of `smbios_bus_width_to_spd_width()` for filling DIMM info. Additionally, ensures dimm_info_util.c file is getting compiled for romstage. TEST=dmidecode -t 17 output Total Width and Data Width as expected. Change-Id: I7fdc19fadc576dec43e12f182fe088707e6654d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimizationJohn Zhao2021-10-291-0/+59
| | | | | | | | | | | | | | | | | | The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency optimization. This change adds additional ACPI DSM function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the USB4/TBT topology which has the same implementation on Tiger Lake in commit I5a19118b75ed0a78b7436f2f90295c03928300d7. BUG=b:199757442 TEST= It was validated that the first connected device waits only 50ms instead of 100ms and all functions work on Alder Lake platform boards. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0c8977c96de27ab0e554469eba658660975b8493 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/apollolake: Fix BUG-message when checking for XDCI deviceWerner Zeh2021-10-291-3/+1
| | | | | | | | | | | | | | | | | | | | | | The current check for XDCI enabled uses a static device path to an internal PCI device at a very late point in the boot flow. At this time the devicetree has been processed and disabled devices have been already removed. If this device (00:15.1, XDCI) is disabled in devicetree this will trigger the message 'BUG: check_xdci_enable requests hidden 00:15.1' in the log. This looks weird and is wrong since it is not a bug to disable this device when it is not needed. To avoid this look up the devicetree by a tree walk instead of using a static value for the devicetree. Change-Id: If193be724299c4017e7e10142fac8db9fac44383 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/icelake: select SOC_INTEL_COMMON_BLOCK_ACPI_GPIOArthur Heymans2021-10-291-0/+1
| | | | | | | | | | | | The Intel icelake rvp boards actually rely on this but this failure was hidden in a runtime error instead of a compile time error, due to weakly linked functions. Change-Id: Idbbe774efa1515ce1d34ce2ce8f87953300a3312 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58662 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/acpi: Correct IPC sub command for reading LPM requirementEthan Tsao2021-10-272-1/+3
| | | | | | | | | | | | | | | | | | | Modify IPC sub command to 2 from 0 for reading LPM requirement from PMC. Reference: https://github.com/otcshare/CCG-ADL-Generic-Full ClientOneSiliconPkg\Include\Register\PmcRegs.h #define V_PMC_PWRM_IPC_SUBCMD_GEN_COMM_READ 2 It is consumed in below. ClientOneSiliconPkg\IpBlock\Pmc\Library\PeiDxeSmmPmcLib\PmcLib.c Change-Id: I58509f14f1e67472adda78e65c3a2e3ee9210765 Signed-off-by: Ethan Tsao <ethan.tsao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/common/block/graphics: add missing GPU PCI IDsFelix Held2021-10-271-0/+2
| | | | | | | | | | | | | | | Since the iGPU PCI device IDs for AMD Renoir (family 17h, model 60h) and Lucienne (family 17h, model 68h) are already defined in pci_ids.h, also add them to the pci_device_ids list in the common AMD graphics support block. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1c554d21eece182ecea7b09b45b7aa8a733425d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* cpu/x86/Kconfig.debug_cpu: drop HAVE_DISPLAY_MTRRS optionFelix Held2021-10-261-1/+0
| | | | | | | | | | | | | | | | | Since all x86 CPUs in tree have MTRR support, there is no need to guard the DISPLAY_MTRRS option with HAVE_DISPLAY_MTRRS. Also all x86 CPUs/SoCs have a display_mtrrs call at least somewhere in their code, so selecting the DISPLAY_MTRRS option will always have an effect. All SoCs that don't select RESET_VECTOR_IN_RAM have the postcar stage where it gets called. The two AMD SoCs that select RESET_VECTOR_IN_RAM use the FSP2 driver which contains plenty of display_mtrrs calls. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2894689ce58e7404d9d5a894f3c288bc4016ea19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/intel/quark/Kconfig: don't unselect CPU_X86_LAPICFelix Held2021-10-261-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel Quark SoC does have a LAPIC on its x86 CPU core, so we should select CPU_X86_LAPIC. This will additionally include the Makefile from cpu/x86/lapic. Since none of AP_IN_SIPI_WAIT, LEGACY_SMP_INIT and UDELAY_LAPIC gets selected, only the boot_cpu.c and lapic.c targets will be added to the build. Since SMP isn't set, adding the boot_cpu.c target won't change the resulting binary of a timeless build, since the only function inside will be removed by the compiler's pre-processor in the !SMP case. So the only thing that will change the resulting binary is the addition of the lapic.c target. From this target only the function cpu_get_lapic_addr will be used which overrides the weak implementation in acpi/acpi.c. The call in arch/x86/mpspec.c can be ignored, since GENERATE_MP_TABLE isn't selected. So this change will result in the LAPIC address in the MADT being changed from 0 to to LAPIC_DEFAULT_BASE. Since the documentation of the Quark SoC mentions that it has a LAPIC on its one x86 core, this should work. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f163bd608f0548abb0e8de90843d2a796b8ef6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 11:22:42 +0000