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* soc/intel/../thermal: Fix return type of `pch_get_ltt_value()`Subrata Banik2021-11-171-1/+1
* lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preloadRaul E Rangel2021-11-163-21/+0
* qualcomm/sc7280: gpio: Support eGPIO schemeTaniya Das2021-11-162-1/+5
* soc/intel/../thermal: Drop `ltt_value` local variableSubrata Banik2021-11-161-5/+2
* soc/mediatek/mt8186: add early initialization for eMMCRex-BC Chen2021-11-162-2/+5
* soc/mediatek/mt8186: Configure eMMC and SD CardWenbin Mei2021-11-163-3/+110
* soc/mediatek/mt8195: Add message string when using _Static_assertFlora Fu2021-11-161-2/+4
* soc/intel/alderlake: Fix build failure with enabled CSE stitchingBernardo Perez Priego2021-11-151-17/+17
* sc7280: Add CPUCP firmware supportRavi Kumar Bokka2021-11-157-3/+101
* soc/amd/common/block: Add spi_hw mutexRaul E Rangel2021-11-154-1/+27
* Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen2021-11-153-0/+5
* soc/intel/alderlake: Disable VT-d for early siliconsMeera Ravindranath2021-11-151-0/+9
* amdfwtool: Set soc name for StoneyridgeZheng Bao2021-11-151-0/+2
* soc/amd/stoneyridge/include/pci_devs: remove unused DEVID definesFelix Held2021-11-151-34/+21
* soc/intel/tigerlake: Add config option for S3 ACPISean Rhodes2021-11-155-123/+186
* soc/intel/tigerlake/apci: Only use SCM for ChromeOSSean Rhodes2021-11-151-0/+7
* mb/google/corsola: Add VMCH and VMC for regulator interfaceRex-BC Chen2021-11-151-0/+2
* soc/mediatek/mt8186: Add support for regulator VMCH and VMCRex-BC Chen2021-11-152-0/+124
* soc/mediatek/mt8186: Add AUXADC driver supportGuodong Liu2021-11-153-0/+49
* soc/mediatek/mt8186: add GIC pre-initialization functionRex-BC Chen2021-11-154-0/+36
* soc/mediatek/mt8186: add USB supportRex-BC Chen2021-11-154-2/+56
* mb/google/corsola: Implement regulator interfaceRex-BC Chen2021-11-151-1/+2
* soc/mediatek/mt8186: add SPM register definitionsRex-BC Chen2021-11-151-0/+533
* soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMARex-BC Chen2021-11-154-11/+15
* soc/mediatek: move functions of mmu operation to common folderRex-BC Chen2021-11-158-66/+28
* soc/mediatek/mt8186: Add support for PMIC MT6366James Lo2021-11-158-4/+1553
* soc/mediatek: change help text of FLASH_DUAL_READRex-BC Chen2021-11-153-3/+3
* Add ENV_STAGE_SUPPORTS_SMP to clean up spinlock stubsKyösti Mälkki2021-11-131-15/+0
* mb/google/guybrush: Add variant_espi_gpio_tableRob Barnes2021-11-132-1/+6
* sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMARaul E Rangel2021-11-131-1/+2
* soc/amd/psp_verstage: Reboot on verstage_soc_early_init failRob Barnes2021-11-132-2/+9
* soc/intel/xeon_sp: Fix size_t type mismatch in print statementPaul Menzel2021-11-131-1/+1
* soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDsTracy Wu2021-11-121-0/+3
* soc/mediatek/mt8195: Add APU device apc driverFlora Fu2021-11-125-0/+330
* soc/amd/cezanne: Use LZ4 for FSP-SRaul E Rangel2021-11-121-1/+1
* soc/amd/cezanne: Preload FSP-SRaul E Rangel2021-11-122-0/+12
* soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMARaul E Rangel2021-11-121-1/+9
* lynxpoint/broadwell: Use `azalia_codecs_init()`Angel Pons2021-11-112-15/+4
* haswell/lynxpoint/broadwell: Use `azalia_codec_init()`Angel Pons2021-11-112-5/+4
* lynxpoint/broadwell: Use `azalia_program_verb_table()`Angel Pons2021-11-111-1/+1
* soc/intel: move SGX ACPI code to block/acpiMichael Niewöhner2021-11-116-59/+68
* soc/mediatek/mt8195: fix apusys coding defectsFlora Fu2021-11-111-4/+4
* Spell Intel Cooper Lake-SP with a spacePaul Menzel2021-11-112-2/+2
* arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik2021-11-113-24/+5
* soc/amd/cezanne/fsp_m_parameters: add curly braces around else blockFelix Held2021-11-101-2/+2
* Rename ECAM-specific MMCONF KconfigsShelley Chen2021-11-1040-66/+66
* soc/amd/cezanne,picasso/include/southbridge: use bitwise or in definesFelix Held2021-11-102-6/+6
* soc/amd/cezanne,picasso/include/southbridge: fix typo in defineFelix Held2021-11-092-2/+2
* soc/intel/alderlake: Enable Intel FIVR RFI settingsWisley Chen2021-11-092-0/+42
* soc/intel: generate SSDT instead of using GNVS for SGXMichael Niewöhner2021-11-0910-50/+45
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