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* soc/intel/common: Include Alder Lake device IDsSubrata Banik2020-08-0518-2/+226
* soc/intel/skylake: Add RMRRs after all DRHDsAngel Pons2020-08-041-11/+18
* soc/intel/broadwell: Add RMRRs after all DRHDsAngel Pons2020-08-041-11/+18
* soc/intel/apollolake/acpi.c: Add RMRRs after all DRHDsAngel Pons2020-08-041-8/+13
* soc/amd/picasso/acpi: clean up global NVSFelix Held2020-08-042-40/+20
* soc/intel/baytrail: Factor out `acpi_fill_madt()`Angel Pons2020-08-041-0/+15
* soc/amd/picasso: set is_rv to 1 for RV familyAkshu Agrawal2020-08-031-0/+8
* soc/intel/baytrail: Add MRC SMBus workaroundMate Kukri2020-08-031-1/+17
* soc/intel/xeon_sp/cpx: configure STACK_SIZEJonathan Zhang2020-08-031-0/+4
* soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2Jonathan Zhang2020-08-035-21/+22
* src/soc/intel/jasperlake: Update SD card ACPI deviceAamir Bohra2020-08-032-0/+73
* Change all assert(0) to BUG()Julius Werner2020-08-034-4/+4
* qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32Julius Werner2020-08-031-3/+3
* soc/intel/tigerlake: Invoke PCIe root port swappingCaveh Jalali2020-08-031-0/+10
* soc/intel/baytrail/northcluster.c: Clean up commentsAngel Pons2020-08-021-3/+6
* soc/intel/baytrail/sata.c: Fix SATA init sequenceAngel Pons2020-08-021-4/+2
* soc/intel/baytrail: Add native refcode replacementMate Kukri2020-08-028-32/+756
* soc/intel/baytrail/northcluster.c: Rename variableAngel Pons2020-08-021-3/+3
* soc/intel/baytrail/northcluster.c: Tidy up long linesAngel Pons2020-08-021-4/+2
* soc/intel/braswell/northcluster.c: Tidy up long linesAngel Pons2020-08-021-6/+3
* soc/intel/braswell/northcluster.c: Rename macroAngel Pons2020-08-021-12/+12
* soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecatedSubrata Banik2020-08-013-12/+2
* soc/intel/cannonlake: Fix DMAR when no iGPU is presentPatrick Rudolph2020-07-311-8/+11
* soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZEJonathan Zhang2020-07-311-0/+11
* smbios: Fix type 17 for Windows 10Patrick Rudolph2020-07-301-53/+34
* mb/amd,google/mandolin,zork: Set EFS SPI platform configMatt Papageorge2020-07-301-0/+7
* amd/common/block/spi: Add EFS SPI configurations to KconfigMatt Papageorge2020-07-301-0/+43
* soc/amd/picasso: Split ops for internal and external PCIe GPP bridgesFurquan Shaikh2020-07-301-4/+20
* soc/intel/tigerlake: Configure TCSS D3Hot and D3ColdJohn Zhao2020-07-292-4/+10
* soc/intel/skylake: Enable HDA depending on devicetree configurationFelix Singer2020-07-292-2/+3
* soc/intel/skylake: Enable HECI3 depending on devicetree configurationFelix Singer2020-07-292-2/+3
* soc/intel/skylake: Enable eMMC depending on devicetree configurationFelix Singer2020-07-292-2/+3
* soc/intel/skylake: Enable TraceHub depending on devicetree configurationFelix Singer2020-07-292-2/+3
* soc/intel/skylake: Enable SMBus depending on devicetree configurationFelix Singer2020-07-292-5/+4
* soc/intel/skylake: Enable LAN depending on devicetree configurationFelix Singer2020-07-292-3/+3
* soc/intel/skylake: Enable SATA depending on devicetree configurationFelix Singer2020-07-292-3/+3
* src/soc/rockchip: Add missing <{stddef,stdint}.h>Elyes HAOUAS2020-07-292-0/+3
* soc/intel/tigerlake: Set default USB3 de-emphasis to -3.5dBDuncan Laurie2020-07-291-1/+1
* soc/intel/jasperlake: Clean up report_cpu_info() functionUsha P2020-07-291-24/+4
* util/apcb: Strip SPD manufacturer informationRob Barnes2020-07-291-0/+2
* src/soc/samsung/exynos{5250,s5420}: Add missing <{stddef,stdint}.h>Elyes HAOUAS2020-07-292-0/+4
* soc/amd/picasso: Add controls for SMT and downcoringMarshall Dawson2020-07-282-0/+11
* src/soc/amd: Add include <types.h>Elyes HAOUAS2020-07-285-4/+5
* soc/amd/picasso: Enable VBNV_BACKUP_TO_FLASH for psp_verstageMartin Roth2020-07-281-1/+1
* soc/amd/picasso: Init SPI in psp_verstageMartin Roth2020-07-281-0/+2
* soc/amd/picasso/Makefile.inc: force an error if PSPBTLDR_FILE is not setRonald G Minnich2020-07-281-1/+1
* src: Never set ISA Enable on PCI bridgesAngel Pons2020-07-282-4/+2
* soc/intel/braswell/fadt.c: Use `ACPI_ADDRESS_SPACE_IO` macroAngel Pons2020-07-281-5/+5
* broadwell: Factor out PIRQ routing from devicetreeAngel Pons2020-07-282-29/+11
* soc/intel/cannonlake: Configure SataPwrOptEnable only if SATA is enabledFelix Singer2020-07-281-5/+1
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