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path: root/src/southbridge/amd/cimx/sb800/late.c
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* sb/amd: Remove dropped platformsArthur Heymans2022-11-071-439/+0
* sb/amd/cimx: Fix some white spaces issuesElyes Haouas2022-07-181-2/+2
* src: Make PCI ID define names shorterFelix Singer2022-03-071-18/+18
* ACPI: Have common acpi_fill_mcfg()Kyösti Mälkki2021-10-181-8/+0
* sb/amd/cimx/sb800: Clear IOAPIC vectors only onceKyösti Mälkki2021-10-171-1/+0
* southbridge/amd: Create ACPI MCFG MMCONFIGAngel Pons2021-06-211-1/+3
* src/southbridge: Drop unneeded empty linesElyes HAOUAS2020-09-211-3/+0
* Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"Nico Huber2020-06-091-1/+1
* src: Use pci_dev_ops_pci where applicableAngel Pons2020-06-061-9/+5
* sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS2020-06-061-1/+1
* src/sb: Use 'print("%s...", __func__)'Elyes HAOUAS2020-05-261-2/+2
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh2020-05-021-1/+1
* Drop explicit NULL initializations from `device_operations`Elyes HAOUAS2020-04-051-7/+0
* src/southbridge: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-041-13/+2
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-2/+0
* treewide: capitalize 'USB'Elyes HAOUAS2020-02-261-1/+1
* sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possibleMichał Żygowski2020-01-051-3/+3
* device: Use scan_static_bus() over scan_lpc_bus()Nico Huber2019-10-081-1/+1
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-3/+3
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-041-0/+1
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-011-0/+1
* southbridge/amd/cimx: Drop unused functionsKyösti Mälkki2019-01-101-14/+0
* src: Move constant to the right side of comparisonElyes HAOUAS2019-01-071-3/+3
* src/southbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-07-091-1/+1
* src: Get rid of unneeded whitespaceElyes HAOUAS2018-06-141-6/+6
* cimx/sb800: Use PCI_DEVFN()Kyösti Mälkki2018-05-211-15/+15
* sb/amd/cimx/sb800: Get rid of device_tElyes HAOUAS2018-05-201-4/+4
* AGESA_LEGACY: Apply final cleanup and file removalsKyösti Mälkki2018-01-231-3/+2
* AMD CIMx SB800: late.c: Use variable `device` from for loop conditionPaul Menzel2018-01-141-3/+2
* device: acpi_name() should take a const struct deviceAaron Durbin2017-09-141-1/+1
* AGESA CIMX: Remove empty set_pcie_(de)resetKyösti Mälkki2017-09-121-8/+0
* AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpartKyösti Mälkki2017-08-021-0/+2
* southbridge/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-301-3/+3
* cimx/sb800: Log southbridge call-sitesKyösti Mälkki2017-04-031-0/+7
* southbridge/amd: Add LPC bridge acpi path for Family14 and SB800Tobias Diedrich2017-02-221-0/+16
* src/southbridge: Code formatingElyes HAOUAS2016-08-311-27/+27
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* amd/cimx/sb800/late.c: Add comment in `sb800_init()`Paul Menzel2015-10-291-0/+1
* SB800: Port to 64bitStefan Reinauer2015-07-301-7/+8
* devicetree: Discriminate device ops scan_bus()Kyösti Mälkki2015-06-041-1/+1
* acpi: Remove monolithic ACPIVladimir Serbinenko2015-05-261-1/+1
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-1/+1
* kbuild: automatically include southbridgesStefan Reinauer2015-04-271-1/+1
* bootstate: use structure pointers for scheduling callbacksAaron Durbin2015-03-181-4/+1
* AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pinsKyösti Mälkki2015-02-231-1/+1
* x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert2015-02-151-4/+5
* AMD cimx/sb800: Initially enable all GPP portsKyösti Mälkki2015-02-141-17/+2
* AMD cimx/sb800: Move cimx init for ramstageKyösti Mälkki2015-02-141-2/+11
* AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configurationKyösti Mälkki2015-02-141-45/+9
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