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coreboot.git
24.02_branch
4.1
4.10_branch
4.11_branch
4.12_branch
4.14_branch
4.15_branch
4.16_branch
4.18_branch
4.19_branch
4.2
4.20_branch
4.22_branch
4.3
4.4
4.8_branch
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path:
root
/
src
/
southbridge
/
amd
/
cimx
/
sb900
/
reset.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
cpu/nb/sb: Remove fam12
Joe Moore
2019-11-20
1
-48
/
+0
*
arch/io.h: Drop unnecessary include
Kyösti Mälkki
2019-03-04
1
-1
/
+0
*
device/pci: Fix PCI accessor headers
Kyösti Mälkki
2019-03-01
1
-0
/
+1
*
AGESA: Drop CONFIG_CBB and CONFIG_CDB
Kyösti Mälkki
2019-01-14
1
-2
/
+3
*
sb/amd/cimx/sb[89]00: Use CF9 reset
Nico Huber
2018-10-22
1
-15
/
+4
*
Consolidate reset API, add generic reset_prepare mechanism
Julius Werner
2017-06-13
1
-2
/
+2
*
src/southbridge: Code formating
Elyes HAOUAS
2016-08-31
1
-1
/
+1
*
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-31
1
-4
/
+0
*
Remove address from GPLv2 headers
Patrick Georgi
2015-05-21
1
-1
/
+1
*
southbridge: Trivial - drop trailing blank lines at EOF
Edward O'Callaghan
2014-07-08
1
-1
/
+0
*
AMD cimx sb700/sb800/sb900: Fix NODE_PCI and use of MAX_PHYSICAL_CPUS
Kyösti Mälkki
2014-04-20
1
-5
/
+1
*
Add pci_devfn_t and use with __SIMPLE_DEVICE__
Kyösti Mälkki
2013-08-24
1
-1
/
+1
*
Add directive __SIMPLE_DEVICE__
Kyösti Mälkki
2013-08-01
1
-3
/
+3
*
AMD southbridges: Move HAVE_HARD_RESET
Kyösti Mälkki
2013-06-17
1
-0
/
+67