coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	src/southbridge: Drop unneeded empty lines	Elyes HAOUAS	2020-09-21	1	-1/+0
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	5	-5/+0
*	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons	2020-04-04	5	-65/+10
*	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi	2020-03-17	5	-6/+0
*	{soc,southbridge}///acpi: Add possibility to disable S4	Wim Vervoorn	2020-01-22	1	-0/+3
*	AGESA,binaryPI: Replace use of __PRE_RAM__	Kyösti Mälkki	2019-08-20	2	-6/+0
*	src/southbridge/amd: Remove unused variables	Elyes HAOUAS	2019-04-25	1	-2/+0
*	src: Use 'include <string.h>' when appropriate	Elyes HAOUAS	2019-03-20	1	-1/+0
*	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner	2019-03-08	1	-1/+1
*	device/pci: Fix PCI accessor headers	Kyösti Mälkki	2019-03-01	1	-0/+1
*	AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON	Kyösti Mälkki	2019-01-14	1	-1/+0
*	reset: Finalize move to new API	Nico Huber	2018-10-31	1	-0/+35
*	src/southbridge: Use "foo bar" instead of "foo bar"	Elyes HAOUAS	2018-07-09	2	-4/+4
*	sb/amd/common: Get rid of device_t	Elyes HAOUAS	2018-05-20	1	-2/+2
*	AGESA f15 cimx/sb700: Remove unused chips code	Kyösti Mälkki	2018-01-24	1	-1/+0
*	AGESA binaryPI: Consolidate and fix sleep states	Kyösti Mälkki	2017-08-23	1	-0/+40
*	src/amd: Add common definition of AMD ACPI MMIO address	Timothy Pearson	2017-01-05	1	-0/+22
*	src/southbridge: Code formating	Elyes HAOUAS	2016-08-31	1	-1/+1
*	southbridge/amd: add support for Bolton FCH	Felix Held	2015-11-20	1	-0/+1
*	tree: drop last paragraph of GPL copyright header	Patrick Georgi	2015-10-31	2	-8/+0
*	southbridge/amd/pi: Add support for new AMD southbridge Kern	WANG Siyuan	2015-06-13	1	-0/+1
*	Remove address from GPLv2 headers	Patrick Georgi	2015-05-21	2	-2/+2
*	kbuild: automatically include southbridges	Stefan Reinauer	2015-04-27	3	-0/+259