| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | sb/amd/pi/hudson: remove unused Bolton PI FCH code | Felix Held | 2021-04-11 | 1 | -8/+0 |
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | src/southbridge: Use SPDX for GPL-2.0-only files | Angel Pons | 2020-04-04 | 1 | -13/+2 |
| * | src (minus soc and mainboard): Remove copyright notices | Patrick Georgi | 2020-03-17 | 1 | -1/+0 |
| * | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner | 2019-03-08 | 1 | -3/+3 |
| * | src: Get rid of unneeded whitespace | Elyes HAOUAS | 2018-06-14 | 1 | -1/+1 |
| * | AMD Bettong: refactor PCI interrupt table | WANG Siyuan | 2015-11-20 | 1 | -1/+7 |
| * | tree: drop last paragraph of GPL copyright header | Patrick Georgi | 2015-10-31 | 1 | -4/+0 |
| * | southbridge/amd/pi: Add support for new AMD southbridge Kern | WANG Siyuan | 2015-06-13 | 1 | -0/+5 |
| * | Remove address from GPLv2 headers | Patrick Georgi | 2015-05-21 | 1 | -1/+1 |
| * | southbridge/amd/pi: Add the bolton definitions | Dave Frodin | 2015-02-05 | 1 | -4/+15 |
| * | southbridge/amd/pi: Rename Avalon to Hudson | Dave Frodin | 2015-01-27 | 1 | -0/+72 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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