summaryrefslogtreecommitdiffstats
path: root/src/southbridge/intel/bd82x6x/usb_xhci.c
Commit message (Expand)AuthorAgeFilesLines
* sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetreeFelix Held2023-12-061-9/+1
* src: Make PCI ID define names shorterFelix Singer2022-03-071-1/+1
* sb/intel/bd82x6x: Use PCI bitwise opsAngel Pons2020-06-101-3/+1
* src: Use pci_dev_ops_pci where applicableAngel Pons2020-06-061-5/+1
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* Drop explicit NULL initializations from `device_operations`Elyes HAOUAS2020-04-051-1/+0
* src/southbridge: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-041-14/+2
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-1/+0
* southbridge/intel: Tidy up preprocessor and headersKyösti Mälkki2019-08-211-0/+1
* {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem()Subrata Banik2019-03-211-13/+1
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-011-0/+1
* sb/intel/bd82x6x: Get rid of device_tElyes HAOUAS2018-06-041-1/+2
* device: acpi_name() should take a const struct deviceAaron Durbin2017-09-141-1/+1
* sb/intel/bd82x6x: Fill in acpi_namePatrick Rudolph2017-06-271-0/+6
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-1/+1
* southbrige/intel/bd82x6x: add XHCI overcurrent map configNicolas Reinecke2015-04-201-0/+3
* southbrige/intel/bd82x6x: XHCI replace magic valuesNicolas Reinecke2015-04-191-2/+2
* bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.Vladimir Serbinenko2015-02-011-0/+4
* usbdebug: Move under drivers/usbKyösti Mälkki2014-02-061-1/+1
* Pantherpoint: Add XHCI device initDuncan Laurie2013-03-171-0/+81
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-20 13:02:57 +0000