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* sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstageArthur Heymans2019-10-091-19/+1
* device: Use scan_static_bus() over scan_lpc_bus()Nico Huber2019-10-081-1/+1
* intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki2019-10-013-13/+10
* sb/intel/bd8x62x,i82801gx: Fix PCI bridge subsystem IDsKyösti Mälkki2019-09-301-29/+1
* sb/intel/bd82x6x: Use common final SPI OPs setupArthur Heymans2019-09-303-76/+21
* device/pci: Replace add with bitwise-orKyösti Mälkki2019-09-221-1/+1
* southbridge: Remove not used #include <elog.h>Elyes HAOUAS2019-09-121-1/+0
* southbridge/intel: Tidy up preprocessor and headersKyösti Mälkki2019-08-218-17/+19
* cpu/x86: Separate save_state struct headersKyösti Mälkki2019-08-131-0/+1
* sb/intel/bd82x6x: Add support to disable xHCIPatrick Rudolph2019-07-261-0/+6
* sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph2019-07-192-7/+4
* sb/intel/bd82x6x: Add and use more RCBA definesPatrick Rudolph2019-07-187-115/+176
* arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki2019-07-091-1/+1
* sb/intel/bd82x6x/early_pch.c: Remove variable set but not usedElyes HAOUAS2019-06-211-20/+15
* sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetreeArthur Heymans2019-06-211-0/+22
* sb/intel/bd82x6x/lpc.c: Remove reinitializing the SPI driverArthur Heymans2019-06-181-6/+0
* src/southbridge: Add missing 'include <types.h>'Elyes HAOUAS2019-05-291-1/+3
* sb/intel/*: Delete early_spiPatrick Rudolph2019-05-293-110/+0
* nb/intel/sandybridge: Move DMI init codePatrick Rudolph2019-05-162-204/+7
* sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcrosPatrick Rudolph2019-05-161-162/+164
* sb/intel/sandybridge/early_pch: Make DMI init more readablePatrick Rudolph2019-05-162-71/+137
* src/southbridge: Remove unneeded include <arch/io.h>Elyes HAOUAS2019-05-151-1/+0
* {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macroElyes HAOUAS2019-05-131-2/+2
* sb/bd82x6x: Don't rewrite over BCTRLElyes HAOUAS2019-05-101-3/+0
* sb/intel/bd82x6x: Fix flashconsole after lockdownDan Elkouby2019-05-071-0/+6
* sb/{ICH7,NM10,PCH}: Use common watchdog_off functionElyes HAOUAS2019-05-073-57/+1
* sb/intel/bd82x6x: Use common/rcba.hPatrick Rudolph2019-05-061-18/+14
* {soc, southbridge} : Correct typo in commentFrans Hendriks2019-05-031-1/+1
* sb/intel/bd82x6x: Use system_reset()Elyes HAOUAS2019-04-291-2/+2
* sb/intel/bd82x6x: fix linking for non-native raminit caseMatt DeVillier2019-04-231-1/+2
* nb/intel/sandybridge: Drop pch.h from sandybridge.hPatrick Rudolph2019-04-231-0/+1
* nb/intel/sandybridge: Move southbridge code to bd82x6xPatrick Rudolph2019-04-182-0/+35
* sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph2019-04-164-55/+2
* src: Use include <delay.h> when appropriateElyes HAOUAS2019-04-061-3/+2
* Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner2019-03-251-1/+1
* sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem()Kyösti Mälkki2019-03-251-26/+1
* {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()Subrata Banik2019-03-211-14/+1
* {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem()Subrata Banik2019-03-218-95/+8
* src: Use 'include <string.h>' when appropriateElyes HAOUAS2019-03-202-2/+0
* src: Drop unused '#include <halt.h>'Elyes HAOUAS2019-03-161-5/+3
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-085-19/+19
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-048-7/+8
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-046-6/+0
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-0118-0/+18
* ACPI: Rename FADT model and set it to zeroElyes HAOUAS2019-03-011-1/+1
* sb/intel/bd82x6x: Fix default IRQ mappingNico Huber2019-02-211-27/+60
* buildsystem: Promote rules.h to default includeKyösti Mälkki2019-01-161-1/+0
* sb/intel: Use common RCBA MACROsPeter Lemenkov2019-01-141-3/+0
* sb/intel: Check for NULL-return of pcidev_on_root()Nico Huber2019-01-131-2/+4
* cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans2019-01-092-25/+0