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path: root/src/southbridge/intel/lynxpoint/pch.h
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* sb/intel/lynxpoint: Remove GPE0_{EN,STS}_2 definesKyösti Mälkki2023-05-141-2/+0
* sb/intel/lynxpoint: Add native PCH initAngel Pons2022-12-161-0/+7
* sb/intel/lynxpoint: Add native thermal initAngel Pons2022-12-161-0/+1
* sb/intel/lynxpoint: Add native USB initAngel Pons2022-12-161-0/+49
* haswell/lynxpoint: Add native DMI initAngel Pons2022-12-161-1/+19
* sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki2022-11-281-1/+1
* sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLITKyösti Mälkki2022-11-281-0/+3
* sb/intel/common: Fix GPE0 related register conflictKyösti Mälkki2022-11-171-2/+2
* treewide: Add 'IWYU pragma: export' commentElyes Haouas2022-11-031-2/+1
* src/soc to src/superio: Fix spelling errorsMartin Roth2021-10-051-1/+1
* sb/intel/lynxpoint: Add SerialIO UART console supportAngel Pons2021-06-091-0/+4
* sb/intel/lynxpoint: Add pch_iobp_exec() functionAngel Pons2021-05-201-0/+2
* sb/intel: Drop outdated SMBus I/O BAR commentAngel Pons2021-05-161-8/+0
* sb/intel/lynxpoint: Add and use power state bit macrosAngel Pons2021-04-261-0/+11
* nb/intel/haswell: Move USB config API into Lynx PointAngel Pons2021-03-251-0/+42
* sb/intel/lynxpoint: Move S3 check out of `early_pch_init`Angel Pons2021-03-151-1/+1
* sb/intel/lynxpoint: Replace HPET_ADDRAngel Pons2021-03-151-2/+0
* sb/intel/lynxpoint/pch.h: Guard macro parametersAngel Pons2021-02-121-10/+10
* sb/intel/lynxpoint: Drop invalid SATA registersAngel Pons2020-11-231-41/+1
* sb/intel/lynxpoint: Correct SATA DTLE IOBP registersAngel Pons2020-11-071-4/+4
* sb/intel/lynxpoint: Drop unnecessary `UL` suffixAngel Pons2020-10-311-3/+3
* sb/intel/lynxpoint: Use common code to generate HPET tableAngel Pons2020-10-311-1/+0
* sb/intel/lynxpoint: Do not determine PCH type at runtimeAngel Pons2020-09-141-1/+5
* sb/intel/lynxpoint: Move IOBP API to its own compilation unitAngel Pons2020-08-121-3/+0
* sb/intel/lynxpoint: Remove incorrect RCBA registersAngel Pons2020-08-121-34/+0
* sb/intel: Remove inexistent references to IDE controllerAngel Pons2020-08-121-2/+1
* sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons2020-07-201-2/+1
* sb/intel/lynxpoint: Define SerialIO devfnsAngel Pons2020-07-141-0/+11
* sb/intel/lynxpoint: Add PCH platform type functionAngel Pons2020-07-121-5/+8
* haswell: Drop GPIO indirection layersAngel Pons2020-07-091-1/+1
* sb/intel/lynxpoint: Drop RCBA reg script mechanismAngel Pons2020-07-091-40/+0
* haswell: Turn RCBA configuration into a functionAngel Pons2020-07-091-2/+2
* device/smbus_host: Declare common early SMBus prototypesKyösti Mälkki2020-06-221-5/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh2020-05-021-1/+1
* src/southbridge: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-041-13/+2
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-2/+0
* sb/intel/common: Declare common smbus_base() and enable_smbus()Kyösti Mälkki2020-01-141-1/+0
* sb/intel/common: Add smbus_set_slave_addr()Kyösti Mälkki2020-01-091-1/+0
* src/southbridge: change "unsigned" to "unsigned int"Martin Roth2019-10-301-1/+1
* intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki2019-10-011-4/+0
* southbridge/intel: Tidy up preprocessor and headersKyösti Mälkki2019-08-211-13/+5
* soc/intel: Rename some SMM support functionsKyösti Mälkki2019-08-151-8/+0
* sb/intel/lynxpoint: Use common final SPI OPs setupArthur Heymans2019-07-081-36/+0
* sb/intel/*: Delete early_spiPatrick Rudolph2019-05-291-1/+0
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-2/+2
* sb/intel: Use common RCBA MACROsPeter Lemenkov2019-01-141-19/+2
* Kconfig: Unify power-after-failure optionsNico Huber2019-01-061-4/+0
* sb/intel/lynxpoint: Handle H81 only having 6 PCIe root portsTristan Corrick2018-12-281-0/+1
* sb/intel/common: Create a common PCH finalise implementationTristan Corrick2018-12-031-1/+0
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