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* build system x86: deprecate bootblock_lds and ldscripts variablesPatrick Georgi2015-04-044-4/+4
| | | | | | | | | | | | | | | | | Instead of keeping this separate variable around, add linker scripts to the $(class)-y source lists and let the build system sort things out. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I4af687becf2971e009cb077debc902d2f0722cfb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9289 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* southbridge/amd/pi: Add initialization of 8254 and 8259Dave Frodin2015-04-021-0/+8
| | | | | | | | | | | | | This moves the initialization of the 8254 and 8259 out of the (unmerged) lamar mainboard romstage.c file and into the southbridge code as it is done in the other AMD southbridges. Change-Id: I73b375754ee4a9bf15981f2cd31056d7e04db23e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/9182 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
* amd/pi/hudson: INCLUDES was renamed to CPPFLAGS_commonPatrick Georgi2015-04-011-2/+0
| | | | | | | | | | And this path is already included properly elsewhere. Change-Id: I9fc6887fc047a9df1c4cb6fa4f841abb16f6d548 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9174 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* Update hex values to CBFS binary name types in MakefilesMartin Roth2015-03-301-1/+1
| | | | | | | | | | | | | | | | | | These binaries were being added to CBFS using hexadecimal values instead of the CBFS binary type names. The same value was being used in different places for different things. For example, the value 0xAB is used for SPDs, MRC & FSP binaries. This patch uses CBFS type names instead of hex values everywhere a hex value was previously used. Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
* build system: normalize linker script file namesPatrick Georgi2015-03-2810-6/+6
| | | | | | | | | | | | | | | | | We have .lb, .lds, and .ld in the tree. Go for .ld everywhere. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9107 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* CBMEM: Add LATE_CBMEM_INIT guardsKyösti Mälkki2015-03-197-1/+22
| | | | | | | | | | | Our target is to get rid of backup_top_of_ram() and get_top_of_ram() entirely so only declare these with LATE_CBMEM_INIT=y. Change-Id: I54f549fe774996f4d803f9ec527e0fac46f6576f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8749 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
* southbridge/amd/rs780: Remove requirement for CF8/CFC config accessKyösti Mälkki2015-03-191-22/+4
| | | | | | | | | | | | | | | | The AMD RS780 early initialization code originally used the CF8/CFC I/O method for PCI configuration space access. After the default configuration access method was changed to MMIO (http://review.coreboot.org/#q,aad07472), booting would hang at "PCI: pci_scan_bus for bus 01". Fix the problem by changing function rs780_nb_gfx_dev_table() so that it no longer borrows the BAR3 address needed for PCIe MMIO config usage. Change-Id: I8816b94c848e1b50f8c880e5867a96ca2a33a8a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8394 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* bootstate: use structure pointers for scheduling callbacksAaron Durbin2015-03-185-19/+5
| | | | | | | | | | | | | | | | | | | | | | | The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* southbridge/amd/pi: Enable early I/O decode to LPCDave Frodin2015-03-172-0/+59
| | | | | | | | | | | | | The decode of UART addresses down to the LPC bus needs to occur early to allow romstage console messages to be seen. This enables the decode of most of the I/O ports typically seen in a system. Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* Intel common SPI: Fix compilation breakage from refactoringStefan Reinauer2015-03-171-0/+2
| | | | | | | | | | | When the Intel SPI drivers were refactored, compilation for Chrome OS devices broke, because ELOG uses the SPI driver in SMM. Change-Id: If2b2da5d526196ed742e17409b01a381417d0ce8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8701 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* x86 SMM: Replace weak prototypes with weak function stubKyösti Mälkki2015-03-118-58/+36
| | | | | | | | | Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* x86: Fix pointer arithmetic regressions from MMIO changesKevin Paul Herbert2015-02-273-3/+3
| | | | | | | | | | | | | | | | | | | | During the development of commit bde6d30 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer), there were several iterations and patterns tried. An intermediate pattern was the use of u32 pointers, and division by sizeof(u32). Some of these did not get properly changed to pointer types of length 1, causing a regression in the Intel Ibex Peak SATA driver, fixed in commit 9b5f137 (Intel ibexpeak: Fix SATA configuration). Other regressions of this pattern are fixed here. I audited all changes to u32 types, and the other ones are safe. Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Reviewed-on: http://review.coreboot.org/8530 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* amd/sb600: Fix NULL test after use issuePatrick Georgi2015-02-251-2/+2
| | | | | | | | | | Change-Id: Icecbcc1dee837ecfe0dd52bade3b83fdcdd15bad Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8513 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Intel ibexpeak: Fix SATA configurationKyösti Mälkki2015-02-241-1/+1
| | | | | | | | | | It got broken with commit bde6d309. Change-Id: I0d7180b1659da45bf87d4de46b7b387cbc73cd0e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8523 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pinsKyösti Mälkki2015-02-232-1/+2
| | | | | | | | | | | | | | | Some GPIO pins are shared with PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, simply setting 0:14.4 disabled in the devicetree does not work here yet. Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8495 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins)
* nvidia/ck804: Minor cleanup on dead codeKyösti Mälkki2015-02-1612-31/+0
| | | | | | | | | Change-Id: I07f4190ab73ec3468e3738be14d64468e2a05720 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8340 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* nvidia/ck804: Fix redundant configuration definesKyösti Mälkki2015-02-1618-60/+30
| | | | | | | | | | | | | | All code must agree on PCI enumeration for the CK804 device, define these only once. The definition in enable_usbdebug.c was different and was assumed incorrect. Change-Id: I7d25c145afbad41db81a6b9b4f3956ad50fcb9f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8339 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Revert "nvidia/ck804: Add ability to override CK804 base unit ID"Kyösti Mälkki2015-02-164-13/+0
| | | | | | | | | | | | This reverts commit b8716879917c420d9e7e2618e48b1411a0c6bcc8. Use of #ifndef here makes it error-prone and hides errors. Change-Id: I13a999250c80adedb6b3fd4963a862ff106750f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8338 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* acpi: Generate valid ACPI processor objectsTimothy Pearson2015-02-165-5/+5
| | | | | | | | | | | | | | | | | The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8422 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert2015-02-15110-716/+776
| | | | | | | | | | | | On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
* AMD cimx/sb800: Initially enable all GPP portsKyösti Mälkki2015-02-141-17/+2
| | | | | | | | | | | | | PCIe root ports on devices 0:15.0 to 0:15.3 should at first all appear visible in hardware. The real configuration will be done by vendorcode once we call sb_Before_Pci_Init(). Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8387 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD cimx/sb800: Move cimx init for ramstageKyösti Mälkki2015-02-143-21/+11
| | | | | | | | | | | | | | | This has nothing to do with SATA controller. We only need to fill the table with defaults before we parse devicetree for changes to device configuration. Change-Id: Ic4b28b5992ec9bfdf252f61b1c86b0162243cc95 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8386 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configurationKyösti Mälkki2015-02-141-45/+9
| | | | | | | | | | | | | | | | | | | | | | | | A set of pins can be configured for GPIO or (parallel) PCI bridge use. When requested configuration is 0:14.4 enabled, register programming must be done before attempting to enumerate devices behind the bridge. When requested configuration is 0:14.4 disabled, we must not even temporarily enable pins for PCI use to avoid spurious GPIO state changes. As our PCI subsystem currently does not configure visible PCI bridges that are marked disabled, we cannot mark 0:14.4 disabled just yet but need to handle pcengines/apu1 as a special case. Drop related dead code. Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8329 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD cimx/sb800: Fix console outputKyösti Mälkki2015-02-141-7/+0
| | | | | | | | | | | These sb800_enable() messages without newline mess up the log. Change-Id: I1689b68702e08e2a287083835f310f52f495c451 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8384 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* southbridge/amd/pi: Combine and correct the IRQ text stringsDave Frodin2015-02-141-13/+7
| | | | | | | | | | | | | | | This combines the Avalon and Bolton tables of text descriptions of the IRQ assignments. It also corrects the text string for the SD controller on Bolton. Test: This was verified on amd/lamar. Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8374 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* Intel FSP platforms: Fix timestampsKyösti Mälkki2015-02-091-5/+6
| | | | | | | | | | Now that BROKEN_CAR_MIGRATE is fixed we can stash these in CAR. Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8024 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
* southbridge/amd/pi: write_hpet requires additional config optionDave Frodin2015-02-051-2/+2
| | | | | | | | | | | | | This copies what was done in southbridge/amd/agesa in: commit 56f46d8 agesa/family15tn: Switch to per-device ACPI TEST: amd/lamar. Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8288 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* southbridge/amd/pi: Update Kconfig and makefiles for boltonDave Frodin2015-02-053-1/+10
| | | | | | | | | Change-Id: I208c931bdaee572c9df11b35c1e6e9f27609ea6c Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8287 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* southbridge/amd/pi: Add the bolton definitionsDave Frodin2015-02-053-4/+57
| | | | | | | | | | | This adds the PCI and interrupt related definitions for the bolton specific features. Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8286 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* AMD8131: Remove obsolete directoryKyösti Mälkki2015-02-052-117/+0
| | | | | | | | | Change-Id: I875384e55a4a71d1a5c962d128d13356f3befa56 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8335 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* nvidia/ck804: make Message Signaled Interrupts workJonathan A. Kollasch2015-02-031-1/+11
| | | | | | | | | | | | | | | Use HT MSI Mapping capability register at 0xe0 in CK804 HT device to enable HT MSI Mapping so that MSIs work. Prior to this change PCIe devices downstream of the CK804 with MSI enabled would fail to actually assert their interrupt. Tested on msi/ms7135 and winent/mb6047 running Debian GNU/Linux 7.0 (wheezy). Change-Id: I5e0dc8b352f3d04e3b16b899af11d2b908a82850 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8276 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.Vladimir Serbinenko2015-02-012-0/+9
| | | | | | | | | Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/8312 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* southbridge/intel/bd82x6x native usb init: replace some magic valuesNicolas Reinecke2015-01-312-4/+10
| | | | | | | | | | | | Some magic numbers are documented in the PCH datasheet so use them. Change-Id: I15b58ff99b3bc11ac437e5ea74f4f01b7c02032a Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8307 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nvidia/ck804: Enable AMD Family 0Fh/10h dynamic ACPI _PSS objectsTimothy Pearson2015-01-281-0/+11
| | | | | | | | Change-Id: I682e6c34d059ae21f9767302659bdfdbea86bcc8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8285 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* nvidia/ck804: Add ability to override CK804 base unit IDTimothy Pearson2015-01-284-0/+13
| | | | | | | | | Change-Id: Ic1b35b6bdd9c6d9ab672242e40b73aff1d626e81 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8273 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
* nvidia/ck804: Fix FTBFS with AMD Family 10h systemsTimothy Pearson2015-01-281-0/+7
| | | | | | | | | | | | | | | | | The build failure stems from a missing function being called via a chain including setup_ss_table(), set_ht_link_ck804(), and st_ht_link_buffer_counts_chain(); the latter function is only available in the AMD K8 code. It appears that a bunch of K8-specific code snuck into the CK804 and MCP55 southbridge code in GIT commit 968bbe89 and GIT commit d4b278c0. Change-Id: I85d005edba44c503c49917d4b928e5c9c5900059 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8269 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* nvidia/ck804: Add ability to enable/disable PCIe PME# wake eventsTimothy Pearson2015-01-283-0/+16
| | | | | | | | Change-Id: Ie2937dd220464e3b168aa8a50a57c03b6258c189 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8283 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* nvidia/ck804: Fix cosmetics in KconfigTimothy Pearson2015-01-281-3/+2
| | | | | | | | Change-Id: Ic675911f534f07516c838b52c9463e89448d4353 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8291 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* nvidia/ck804: Add ability to bypass register 0x78 initializationTimothy Pearson2015-01-281-0/+2
| | | | | | | | | | | | On the ASUS KFSN4-DRE initializing CK804 0x78 causes an almost immediate soft reset. Leaving the register at its power-on default value appears to have no ill effect on that same board. Change-Id: I833603adea580cb3f4441e35044d1e17d2d67852 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8272 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* southbridge/amd/pi: Clean up whitespace in KconfigDave Frodin2015-01-271-21/+21
| | | | | | | | Change-Id: I4dbccc7d132a14a71107f24124814d30d93d6ece Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8252 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* southbridge/amd/pi: Rename Avalon to HudsonDave Frodin2015-01-2739-15/+15
| | | | | | | | | | | | To maintain consistancy with southbridge/amd/agesa/hudson rename pi/avalon to pi/hudson in advance of adding support for the base hudson southbridge. Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8251 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* southbridge/amd/pi: Correct several path namesDave Frodin2015-01-272-4/+4
| | | | | | | | Change-Id: I247c17516cd06970185e271eccb78528a8de01c1 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8249 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* southbridge/amd/pi: Correct several yangtze/avalon typosDave Frodin2015-01-272-3/+3
| | | | | | | | | | | These were probably accidentally missed when the move from southbridge/amd/agesa/hudson to amd/pi/avalon occured. Change-Id: I4cf6e2f8b25899d6d342452cb1b15e694dae35c8 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* nvidia/ck804/lpc.c: Fix power restoration controlTimothy Pearson2015-01-271-3/+7
| | | | | | | | | | | | | | | | | | | Control bits located by changing tristate power restoration value in proprietary BIOS, booting into Linux, dumping the entire CK804 configuration space, then comparing values against those dumped earlier. "Last state" control bit(s) are unknown at this time. TEST: Boot ASUS KFSN4-DRE with both coreboot power on and power off after power failure settings, then pull power plug / reinsert power plug and verify mainboard behaviour matches setting. Change-Id: I737bdd35632fe786968a1cb8458e56c785363cfa Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8258 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
* southbridge/intel/lynxpoint/me_9.x.c: Avoid unused func warnEdward O'Callaghan2015-01-121-24/+26
| | | | | | | | | | | Put functions in appropriate pre-processor sections to avoid false-positive 'unused function' compiler warnings. Change-Id: Ie4955ee9df6904c38848f46226b53be37d9fa239 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8157 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
* ACPI: Add acpi_is_wakeup_s3() for romstageKyösti Mälkki2015-01-1016-169/+146
| | | | | | | | | | This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8187 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* AMD binaryPI: Drop ramtop via nvramKyösti Mälkki2015-01-102-63/+0
| | | | | | | | | | | | If HAVE_ACPI_RESUME gets implemented, EARLY_CBMEM_INIT is required too. Change-Id: I8c7932297e0938eff629d1e46081ccf3e7690aea Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8185 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* AMD binaryPI 00730F01: Switch to per-device ACPIKyösti Mälkki2015-01-091-0/+10
| | | | | | | | | | Change-Id: Iad31ae3e511c8ebacc973b2d8a8e3bfca719ee7c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7583 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* southbridge: Drop print_ implementation from non-romcc boardsStefan Reinauer2015-01-0641-181/+143
| | | | | | | | | | | | | | | | | Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the southbridge code to use printk() on all non-ROMCC boards. Change-Id: I312406257e66bbdc3940e206b5256460559a2c98 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8110 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
* Drop VIA VT8235 southbridgeStefan Reinauer2015-01-0613-933/+77
| | | | | | | | | | It's unused. Change-Id: Iad3e7aa0f777392c9d65b9fcdd3c1666af31723a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7883 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-04 17:35:54 +0000