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* Intel vendorcode: Add FSP_SMBIOS_MEMORY_INFO_GUIDLee Leahy2015-06-241-0/+6
* Removed unused SOUTHBRIDGE_INTEL_FSP_I89XX expressionsMartin Roth2015-06-071-1/+0
* UEFI: Conditionally define the ASSERT macroLee Leahy2015-05-291-0/+2
* Remove address from GPLv2 headersPatrick Georgi2015-05-212-2/+2
* vendorcode/intel: Add EDK2 header filesLee Leahy2015-04-3015-0/+5162
* vendorcode/intel: Add FSP 1.1 header filesLee Leahy2015-04-292-0/+465
* fsp: Move fsp to fsp1_0Marc Jones2015-04-2446-4/+4
* intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSPYork Yang2015-01-311-5/+10
* vendorcode/intel: remove DebugDeadLoop() from fsptypes.hMartin Roth2015-01-134-28/+8
* Mark non-executable files non-executablePatrick Georgi2014-12-013-0/+0
* vendorcode/intel/fsp: Update FSP_VENDORCODE_HEADER_PATHFEI WANG2014-11-292-7/+7
* intel/fsp_baytrail: add Gold3 FSP supportYork Yang2014-11-211-47/+69
* vendorcode/intel/fsp/baytrail/absf: add Minnow Max absf filesMartin Roth2014-08-112-0/+656
* vendorcode/intel/fsp/rangeley/include: Missing 'fsptypes.h'Edward O'Callaghan2014-08-014-2/+9
* vendorcode/intel: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-0812-12/+0
* vendorcode/intel/fsp/rangeley: remove extra fileMartin Roth2014-05-231-521/+0
* baytrail: Fix some minor errors in FSPDavid Hendricks2014-05-211-8/+1
* build: move include paths where they belongPatrick Georgi2014-05-191-4/+1
* Introduce stage-specific architecture for corebootFurquan Shaikh2014-05-061-1/+4
* Add the Rangeley FSP include & srx directoriesMartin Roth2014-04-1112-0/+2581
* Add the Bay Trail FSP include & srx directoriesMartin Roth2014-04-1113-0/+2248
* Add the ivybridge i89xx FSP include & srx directoriesMartin Roth2014-04-1112-0/+1989
* Update vendorcode/intel/makefile for coming FSPsMartin Roth2014-04-111-4/+7
* Correct file permissions.Idwer Vollering2013-12-079-0/+0
* Add Intel FSP northbridge support Sandybridge and IvybridgeMarc Jones2013-12-0412-0/+1999
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