| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency count | Ryan Chuang | 2021-08-09 | 1 | -0/+3 |
| * | vc/mediatek/mt8195: Improve DRAM stability by impedance tracking | Ryan Chuang | 2021-07-28 | 1 | -1/+5 |
| * | vc/mediatek/mt8195: Remove redundant code | Ryan Chuang | 2021-07-13 | 1 | -10/+1 |
| * | vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings | Ryan Chuang | 2021-07-12 | 2 | -2/+6 |
| * | vc/mediatek/mt8195: add FOR_COREBOOT define | Rex-BC Chen | 2021-07-12 | 1 | -10/+12 |
| * | vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability | Ryan Chuang | 2021-07-07 | 1 | -1/+1 |
| * | vc/mediatek/mt8195: Improve settings of duty calibration | Ryan Chuang | 2021-07-07 | 1 | -9/+17 |
| * | vc/mediatek/mt8195: Fix license headers | Rex-BC Chen | 2021-06-30 | 19 | -717/+28 |
| * | vc/mediatek/mt8195: Allow adjusting DRAM voltage in DRAM calibration | Ryan Chuang | 2021-06-24 | 1 | -17/+26 |
| * | vc/mediatek/mt8195: Fix code indentation | Patrick Georgi | 2021-06-15 | 1 | -2/+2 |
| * | vendor/mediatek: Add MT8195 dram initialization code | Ryan Chuang | 2021-05-14 | 20 | -0/+79998 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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