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* vendorcode/amd/agesa: Add CFLAGS required by CLANGArthur Heymans2022-03-251-0/+5
| | | | | | | | | | | Vendorcode is messy so instead of trying to fix the warnings thrown by clang ignore them on AGESA platforms. Change-Id: I378571c2b7272901761c786c6daec0a403155d4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/intel/edk2/edk2-stable202111: Use fixed size struct elementsSubrata Banik2022-03-181-3/+13
| | | | | | | | | | | | | | | | | | | | Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. Change request here:https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. BUG=b:200113959 TEST=Verified on Meteor Lake platform, without any compilation error Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1f33db43f7932cf6d165d0c70a0e2922dad00a09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vc/google/chromeos/Kconfig: Fix typoAngel Pons2022-03-091-1/+1
| | | | | | | | | | | | heirarchy ---> hierarchy Change-Id: I5cbd77a156852e6f8ad6eafc316ee33f153635b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* timestamps: Rename timestamps to make names more consistentJakub Czapiga2022-03-081-2/+2
| | | | | | | | | | | | | | | | | | This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v3091_00Ronak Kanabar2022-03-071-2/+7
| | | | | | | | | | | | | | | | The headers added are generated as per FSP v3091_00 Previous FSP version was v2511_04 Changes include: - Update MemInfoHob.h BUG=b:222415800 BRANCH=None Change-Id: I260544e0502174ab141fa31ac78ede803b4f161e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* src: Make PCI ID define names shorterFelix Singer2022-03-073-6/+6
| | | | | | | | | | | | | | | | | | Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3054.02Ronak Kanabar2022-02-221-3/+3
| | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v3054.02. Previous FSP version was v2503_00. Changes Include: - UPD Offset Update in FspmUpd.h BUG=b:220076892 BRANCH=None TEST=Build and boot adlnrvp Change-Id: I7b921e2aa467597a1c764fc554e2e83e5bb522e8 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependencyFelix Held2022-02-221-0/+5
| | | | | | | | | | | | Compiling vboot_check.c depends on fmap_config.h already being generated so add this dependency. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1fe2b738d76ae16dee3e1ebdca512264303a481c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v2503_00Ronak Kanabar2022-02-161-3/+55
| | | | | | | | | | | | | | | | | | | | | | | | The headers added are generated as per Alder Lake N FSP v2503_00. Previous FSP version was v2503_00. Change include: Add following Emmc UPDs in Fsps.h - ScsEmmcEnabled - ScsEmmcHs400Enabled - EmmcUseCustomDlls - EmmcTxCmdDelayRegValue - EmmcTxDataDelay1RegValue - EmmcTxDataDelay2RegValue - EmmcRxCmdDataDelay1RegValue - EmmcRxCmdDataDelay2RegValue - EmmcRxStrobeDelayRegValue BUG=b:213828776 BRANCH=None Change-Id: I617673a0cb12e7165f2f63cce73fff38bc7bf827 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/amd/common/fsp: check fsp image revisionJulian Schroeder2022-02-113-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | Check if FSP binary and coreboot FSP structures (fspmupd.h) match sufficiently. A change in minor number denotes less critical changes or additions to the FSP API that still allow for the boot process to proceed. A change of the AMD image revision major number will halt boot. The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD Picasso, Cezanne and Sabrina APUs. BUG=b:184650244 TEST=build, boot and check fsp image revision info. Example: FSP major = 1 FSP minor = 0 FSP revision = 5 FSP build = 0 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* vendorcode/intel/fsp: Add FSP header file for Alder Lake N FSP v2503_00Ronak Kanabar2022-02-095-0/+7580
| | | | | | | | | | | | | | | | | | | The headers added are generated as per Alder Lake N FSP v2503_00. Changes include: - Add all header files for Alder Lake N FSP. - List of header files: FirmwareVersionInfoHob.h, FspmUpd.h, FspsUpd.h, FspUpd.h, MemInfoHob.h - Select FSP_HEADER_PATH BUG=b:213828776 BRANCH=None Change-Id: I97afa6d47cc825703a8dc82216250bfc5e09dc9b Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner2022-02-073-24/+20
| | | | | | | | | | | | | | | | | | | | | | | | | Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* vc/amd/cezanne: Add support to map UARTsRaul E Rangel2022-02-071-0/+7
| | | | | | | | | | | | | This will allow coreboot to directly write to the UART controller. BUG=b:215599230 TEST=Try mapping the uart on guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibd346cec2994e612f2901bb91d572982ce2ed5e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* soc/amd/cezanne,vc/cezanne: Implement svc_write_postcodeRaul E Rangel2022-02-021-0/+1
| | | | | | | | | | | | | | | | This will allow verstage to write post codes. BUG=b:215425753 TEST=Boot guybrush and verify PSP post codes are printed 22-01-31 15:12:03.214 (S3->S0) 22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* psp_verstage: add new svc for cezanneKangheui Won2022-02-011-0/+22
| | | | | | | | | | | | | | | Add svc_set_platform_bootmode svc to cezanne. PSP will use this information to select proper widevine keybox. BUG=b:211058864 TEST=build guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* vc/amd/agesa: fix out-of-bounds readJason Nien2022-01-262-2/+2
| | | | | | | | | | | | | Fix the out-of-bounds read issue found by Coverity. TEST=none Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I01e134cb6b025bf7cb5030cd9378297d7f6df509 Reported-by: Coverity (CID:1376956) Reviewed-on: https://review.coreboot.org/c/coreboot/+/58803 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: FSP: Add UPD entry for eDP tuningZheng Bao2022-01-251-1/+8
| | | | | | | | | | | | | | | | | The FSP gets these values from the UPD and sets the internal values. The document about eDP tuning is attached in issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Cq-Depend: chrome-internal:4303901 Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* vc/amd/fsp/sabrina: add as a copy of vc/amd/fsp/cezanneFelix Held2022-01-2513-0/+1284
| | | | | | | | | | | | | | | | The AMD Sabrina SoC will be using the FSP driver to call into the corresponding FSP binary to do its part of for the silicon initialization, so we need an initial set of FSP headers for the AMD Sabrina SoC code to build. Since the FSP interface for this SoC won't be too different from the Cezanne FSP interface, we'll start with a copy of the Cezanne FSP headers and update/replace them as soon as the proper FSP headers for Sabrina will be available. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib3bf50598efe60673b81cf99da491866fb5dc121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro2022-01-132-77/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2511_04 Previous FSP version was v2471_02 Changes include: - UPDs description update in FspsUpd.h and FspmUpd.h - Adjust UPD Offset in FspmUpd.h - Name change of UPDs in FspmUpd.h and FspsUpd.h - Copyright year is updated in FspmUpd.h and FspsUpd.h - Updated spd_upds and dq_upds structure variables in meminit.c - Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask in fsp_params.c BUG=b:213959910 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4448696, chrome-internal:4445910 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: I39646c6812afbf622171361b8206daeacdaafac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* chromeos: Add an elog for Chrome OS diagnostic bootHsuan Ting Chen2022-01-111-1/+8
| | | | | | | | | | | | | | | | | Add an elog type 0xb6 for Chrome OS diagnostics related events and log the message while booting the diagnostic tool: __func__: Logged diagnostic boot BRANCH=none BUG=b:185551931, b:177196147 TEST=emerge-volteer coreboot vboot_reference Change-Id: Icb675fc431d4c45e4f432b2d12cac6dcfb2d5e3a Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* vendorcode/intel/fsp/elkhartlake: Drop obsolete headersFelix Singer2022-01-016-8501/+0
| | | | | | | | | | | | | Elkhart Lake was hooked up to the FSP repo with commit 79fcadb3c46 (soc/intel/elkhartlake: Use FSP from FSP repo by default) making these headers obsolete. Thus, drop them. Change-Id: I2d6a4d4614ae21d5b8e77eceb85baa13e491c2ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/jasperlake: Add CdClock frequency configSimon Yang2022-01-011-5/+2
| | | | | | | | | | | | | | | | | | | | | | Add a devicetree setting to configure the CdClock (Core Display Clock) frequency through a FSP UPD. Because the value for this UPD's default setting is non-zero and devicetree settings default to 0 if not set, adapt the devicetree values so that the value for the UPD's default setting is used when the devicetree setting is zero. Also update the comment describing the FSP UPD in the header file FspsUpd.h to match the correct CdClock definition. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang@intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Revert "Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP ↵Tim Wawrzynczak2021-12-262-9/+8
| | | | | | | | | | | | | | | | v2471_02"" This reverts commit a4dddfc3a3a48727ebcec727a0b1fd87eb4c14ad. Reason for revert: Ready to land FSP 2471.02 Change-Id: I2d858edee2eb24506c3e55a1cb808a1ccbd58da2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
* ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki2021-12-236-16/+14
| | | | | | | | | | | | Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02"Nick Vaccaro2021-12-212-8/+9
| | | | | | | | | | | | | | | | | This reverts commit ae0ea32c52905d6bcb527b04727463bc2d1b9e09. This change should not have merged until the 2471_02 FSP change is ready for merge. BUG=b:211481222 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0 to kernel. Change-Id: Iae5b0c53ace196053e1e155efd2e08f438979ba7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02Ronak Kanabar2021-12-132-9/+8
| | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2471_02. Previous FSP version was v2422_01. Changes Include: - UPDs description update in FspsUpd.h - Adjust UPD Offset in FspmUpd.h and FspsUpd.h BUG=b:208336249 BRANCH=None TEST=Build and boot brya Change-Id: I4d04652c06a1c1823d3859be209710c273a2ae8c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* vendorcode/intel: Add edk2-stable202111 supportSubrata Banik2021-12-11583-0/+237673
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes (edk2/edk2-stable202111) all required headers for edk2-stable202111 EDK2 tag from EDK2 github project using below command: >> git clone -b edk2-stable202111 https://github.com/tianocore/edk2.git commit hash: bb1bba3d776733c41dbfa2d1dc0fe234819a79f2 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Note: edk2-stable202111 tag is required to adopt FSP 2.3 specification. - Need to add ExtendedImageRevision in FSP_INFO_HEADER structure. - Need to add FSP_NON_VOLATILE_STORAGE_HOB2 header. Change-Id: I786cc05f9a638ac6226ebc8c0eaf1dc8189a4ca4 Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* vendorcode/intel: Rework UDK binding KconfigSubrata Banik2021-12-101-2/+9
| | | | | | | | | | | | | | | | | | | | | coreboot code currently supports different UDK binding as per underlying FSP requirement, example: ICL and TGL uses UDK_2017_BINDING while ADL uses UDK_202005_BINDING Kconfig. These UDK binding Kconfigs are being used to choose the correct UDK_VERSION. This patch introduces `UDK_BASE` Kconfig option so UDK_VERSION if clause don't need to add specific UDK binding Kconfig everytime with introduction of newer UDK bindings in future. Tested with BUILD_TIMELESS=1, Hatch remains identical. Change-Id: I64c51aa06a14f0ce541537363870ac3925b79a68 Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAMRyan Chuang2021-12-011-0/+5
| | | | | | | | | | | | | | | Fix the issue that power consumption of single rank DRAM is greater than dual rank DRAM due to incorrect settings of rank1 CKE. Set rank1 CKE to the correct state to fix this issue. BUG=b:196867407 TEST=DUT can boot to OS. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If336197aea4770dda1332b6e83da8ec9a4f9d77b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* Cezanne FSP wrapper: Sync with PI 1.0.0.5Zheng Bao2021-11-301-0/+3
| | | | | | | | | | | | | | | New PI 1.0.0.5 has more data in HOB of DMI, which has been uploaded to google internal repo. The dismatched size of HOB causes the wrong data tranfer. So the coreboot also need to change. BUG=b:204732649 Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01Ronak Kanabar2021-11-151-26/+28
| | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2422_01. Previous FSP version was v2374_01. Changes Include: - Add CnviDdrRfim UPD in FspmUpd.h - UPDs description update in FspmUpd.h BUG=b:205512463 BRANCH=None TEST=Build and boot brya Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Rename ECAM-specific MMCONF KconfigsShelley Chen2021-11-104-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki2021-11-093-5/+2
| | | | | | | | Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* vc/mediatek/mt8195: Remove unused code and commentsRyan Chuang2021-11-0124-15461/+5041
| | | | | | | | | | | | | | | | | Remove unused code and comment to align with the latest MTK memory reference code which is from MTK internal dram driver code without upstream. version: Ib59134533ced8de09d23dd9f347c934d315166e2 TEST=boot to kernel Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I95ab3cf8809ad22a341ceb7fd53a68e13fb0420d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58635 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for CezanneMatt Papageorge2021-10-111-1/+2
| | | | | | | | | | | | | | | | | | Update UPD to include option for FSP to de-assert PCIe reset GPIOs as specified in the DXIO descriptors. This change requires FSP version 1.0.4 revision 2 otherwise setting this value does affect any FSP behavior. BUG=b:199780346 TEST=Verify toggling this value is reflected in FSP Cq-Depend: chrome-internal:4170351 Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* vc/mediatek/mt8195: fix misleading-indentation errorRex-BC Chen2021-10-081-2/+2
| | | | | | | | | | | Fix misleading-indentation error in dramc_pi_calibration_api.c. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I680e9e6fffaebb23bf1f156a7f614345e952ed95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* vc/mediatek/mt8195: Remove unused codeRyan Chuang2021-09-2913-13577/+6
| | | | | | | | | | | | | | | Remove unused drivers and some fast calibration implementations to align with the latest MTK memory reference code. TEST=boot to kernel Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I2e6be2e16c139e48c65352fe2eabf16bf9cd550a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57978 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2374_01Ronak Kanabar2021-09-282-8/+8
| | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2374_01. Previous FSP version was v2347_00. Changes Include: - Offset change in FspmUpd.h and FspsUpd.h BUG=b:201239436 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4150766 Change-Id: I097e854bcb4033bdaf2498fb97b255e87d3dd70f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57920 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne, vc/amd/fsp/*: Add support for CCP DMA SVC callKarthikeyan Ramasubramanian2021-09-272-0/+29
| | | | | | | | | | | | | | | | | | Add support to access the boot device from PSP through Crypto Co-Processor (CCP) DMA. Implement a SVC call to use CCP DMA on SoCs where it is supported and a stub on SoCs where it is not supported. This provides an improved performance while accessing the boot device and reduces the boot time by ~45 ms. BUG=b:194990811 TEST=Build and boot to OS in guybrush. Perform cold and warm reboot cycling for 250 iterations. Change-Id: I02b94a842190ac4dcf45ff2d846b8665f06a9c75 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/xeon_sp/cpx: Use FSP repoArthur Heymans2021-09-236-1130/+138
| | | | | | | | | | | Some headers in vendorcode are still needed but the UPD definitions can be taken from the FSP repo. Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/xeon_sp/cpx: Rename FSP UPDs using CPPArthur Heymans2021-09-231-8/+0
| | | | | | | | | | | | coreboot expects different names for FSP UPDs so use some CPP to make it happy. Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* vc/amd/sb800: Fix out of bounds shiftPaul Menzel2021-09-201-2/+2
| | | | | | | | | | | | | | | | | | | Fix the two issues below. SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:49:18 ubsan: unrecoverable error. SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:66:18 ubsan: unrecoverable error. Found by: UBSAN Change-Id: Id42e62d35f59793bad10998f14422ab7fb4fc029 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* vc/amd/agesa/Kconfig: Move SPD options out of choiceAngel Pons2021-09-201-2/+2
| | | | | | | | | | | | | The Kconfig options for custom SPD values aren't supposed to be part of the choice block. Change-Id: I12eb1012f94000b14e5d7f1e5123dddf69ac1a94 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57717 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* driver/i2c/max98390: add dsm_param_nameWisley Chen2021-09-141-0/+8
| | | | | | | | | | | | | | | | Maxim driver look for "maxim,dsm_param_name" to load dsm parameter file. dsm param file name consist of {dsm_param_file_name} filled in devicetree, {MAINBOARD_VENDOR} and {MAINBOARD_PART_NUMBER}. => {dsm_param_file_name}_{MAINBOARD_VENDOR}_{MAINBOARD_PART_NUMBER}.bin BUG=b:197076844 TEST=build, and check ssdt Change-Id: I006572d6a6ea55298374c688dfd9d877835da82d Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2347_00Ronak Kanabar2021-09-101-3/+3
| | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2347_00. Previous FSP version was v2265_01. Changes include: - UserBd UPD description update in FspmUpd.h BUG=b:199359579 BRANCH=None TEST=Build and boot brya Change-Id: I5e4dd58e5fb1a744b035a4de96986053a02610d3 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vc/mediatek/mt8195: Remove unused codeRyan Chuang2021-09-032-2029/+1
| | | | | | | | | | | | Remove unused drivers and some fast calibration implementations to align with the latest MTK memory reference code. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I3b235cbceb231898f00fce7905f596eab54ca595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57275 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* wifi: Add support for DSM methods for intel wifi cardSugnan Prabhu S2021-09-021-0/+10
| | | | | | | | | | | | | | Add support for DSM methods as per the connectivity document 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:191720858 TEST=Check the generated SSDT tables for DSM methods Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* wifi: Add support for wifi time average SAR configSugnan Prabhu S2021-09-021-0/+15
| | | | | | | | | | | | | | | | Add support for the WTAS ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the WTAS related configuration values and verified that the SSDT has the WTAS ACPI table. Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* wifi: Add support for per-platform antenna gainSugnan Prabhu S2021-09-021-0/+27
| | | | | | | | | | | | | | | | Add support for the PPAG ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the PPAG related configuration values and verified that the SSDT has the PPAG ACPI table. Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* wifi: Add support for new revisions of SAR table entriesSugnan Prabhu S2021-09-021-41/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing SAR infrastructure supports only revision 0 of the SAR tables. This patch modifies it to extend support for intel wifi 6 and wifi 6e configurations as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf The SAR table and WGDS configuration block sizes were static in the legacy SAR file format. Following is the format of the new binary file. +------------------------------------------------------------+ | Field | Size | Description | +------------------------------------------------------------+ | Marker | 4 bytes | "$SAR" | +------------------------------------------------------------+ | Version | 1 byte | Current version = 1 | +------------------------------------------------------------+ | SAR table | 2 bytes | Offset of SAR table from start of | | offset | | the header | +------------------------------------------------------------+ | WGDS | 2 bytes | Offset of WGDS table from start of | | offset | | the header | +------------------------------------------------------------+ | Data | n bytes | Data for the different tables | +------------------------------------------------------------+ This change supports both the legacy and the new format of SAR file BUG=b:193665559 TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different binaries generated by setting different versions in the config.star Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-20 04:16:11 +0000