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* soc/amd/genoa/include/data_fabric: add VGA decode enable registerFelix Held2023-10-121-0/+14
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf4a1fd61ad1d545b1ea0ab3fcf6c7a3d0260cd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
* mb/google/rex/var/karis: Fix touchscreen HID to ELAN9004Tyler Wang2023-10-121-1/+1
| | | | | | | | | | | | | | | Confirmed with vendor, Elan touchscreen HID should set to "ELAN9004". Correct Elan touchscreen HID to "ELAN9004" for karis. BUG=b:294155897 TEST=Dump the SSDT on karis and check the HID had been modified. Change-Id: I6ebb02540c894460388b9b9fe03f5c4031f8186d Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78266 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* sb/intel/bd82x6x/pcie: Drop register writePatrick Rudolph2023-10-121-3/+1
| | | | | | | | | | | The write to register 0x42 has no effect as at this point all of the bits are read-only. Drop the line. Change-Id: I7293e6eaa2d0bac5efe8316029bdecb04a5586e9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78238 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x/pch: Mark static devices hiddenPatrick Rudolph2023-10-121-0/+4
| | | | | | | | | | | | | | | | | | | Because integrated PCI devices are hidden in chip_ops the PCI enumeration code never sees them. When hiding static devices mark them as hidden so the PCI enumeration no longer complains about them being missing, even though they are present and were working just fine. Test: Disabled southbridge devices no longer appear in "Leftover static devices:" log. Change-Id: Iae70072a85b62a456102190a5f72f4d652ad6d5a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* sb/intel/bd82x6x: Warn about slow PCIe downstream devicesPatrick Rudolph2023-10-121-0/+6
| | | | | | | | | | | | | | | Warn when a device took longer than usual to appear. Use the PDS bit to detect if a root port has a downstream device connected and warn if enumeration failed. Test: On Lenovo X220 all PCIe device are visible, thus the added code path is never taken. Change-Id: I86b498b89d672b239d9951e116dc3680030666a6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78229 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x/pcie: Use definesPatrick Rudolph2023-10-121-7/+7
| | | | | | | | | | | | | Use defines instead of magic values. Test: Lenovo X220 still boots and all PCIe devices are still working. Change-Id: Ie8fc7cc863017da07dd3ed37b487dae18de92b18 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78293 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x: Improve SLCAPPatrick Rudolph2023-10-121-6/+27
| | | | | | | | | | | | | | | | | - Use pci_find_capability() and defines from pci_def.h - Set the 'Hotplug Capable' bit and 'Hot Plug Surprise' bit in SLCAP for hotplugable PCIe slots. - Assign unique slot number and set power limit for PCIe root ports that have a slot connected. For integrated devices clear slot number and power limit. Test: System still boots and all PCIe devices are working. Change-Id: I03aeb0a1ff0041901acc20fe700d3f7995d22366 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* Revert "mb/google/rex/var/screebo: Enable GL9750 invert WP function"Kun Liu2023-10-111-1/+0
| | | | | | | | | | | | | | | | This reverts commit ee4191852abf9b24f822468250c24edb993497c6. Reason for revert: In schematic a sdcard write protection pull-down resistor was added, so need to disable GL9750 invert WP function Change-Id: I00a8f43094d8b3674a4bbaeed24b96aab64b9b75 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78295 Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/amd/genoa: add root complex support codeFelix Held2023-10-112-0/+63
| | | | | | | | | | | This functionality will eventually be used by the common data fabric domain resource reporting code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieedd432c144e53e43d8099ec617a15056bb36fd1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78307 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/genoa/include: add data_fabric.hFelix Held2023-10-111-0/+124
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18871af0a8dbc1423524b681d516476e63b9596a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/amd/onyx: Use BMC SOL by defaultArthur Heymans2023-10-111-0/+4
| | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iefe61d25367bbe5cff0cacbfbafa32607de77d0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/amd/onyx: use AMD SoC UARTVarshit Pandya2023-10-111-0/+1
| | | | | | | | Change-Id: I79ebbcc6a4a3a93e8437ef56aebdcf72f9a3e6ab Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/genoa: Enable uartVarshit Pandya2023-10-115-0/+59
| | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76507 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/genoa: Add GPIO supportVarshit Pandya2023-10-113-0/+40
| | | | | | | | Change-Id: I2e827e9ffbb2ec1be0f1247b77660a9fdeb04f7b Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/genoa: Add SMI supportVarshit Pandya2023-10-112-0/+183
| | | | | | | | | | Add SMI definitions as per Genoa PPR Doc #55901 Change-Id: I491f4075cef8976e4b0762752c9e2e3c2ef886d5 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/genoa: Add GPIO definitionsVarshit Pandya2023-10-111-0/+270
| | | | | | | | | | Add GPIO definitions as per Genoa PPR Doc #55901 Change-Id: I0c4e425699c9a158ca95a1baf94f7756f0b12b44 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/rex/var/karis: Set touchscreen power/reset GPIOs correctlyTyler Wang2023-10-111-2/+6
| | | | | | | | | | | | | | | | | | | | The tochscreen isn't powered on yet when the detection is done, it makes touchscren no function. Set touchscreen power and reset GPIOs correctly in romstage and ramstage to make the detect feature works. BUG=b:303130400 TEST=(1) emerge-rex coreboot (2) Test on karis, touchscreen function works Change-Id: I6c7815b81eb47fb41e58233fde512ac6b9c000a7 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78254 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/common/spi: Fix I/O alignmentPatrick Rudolph2023-10-111-6/+16
| | | | | | | | | | | | | | | | | | | | | | On ICH9 the SPI control register is not naturally aligned and a word write might be split into smaller naturally aligned I/O transactions. As the first byte starts a new SPI transfer, replace the existing word write with two byte writes and write the second byte first. This is required for platforms that do not support unaligned word I/O instructions and would start a SPI transfer while the second byte hasn't reached the control register yet. TEST: Virtual SPI controller on qemu 8.0 doesn't start a transfer early. Change-Id: Id05b1a080911b71b94ef781c6e26d98165f02f67 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* Kconfig: Bring HEAP_SIZE to a common, large valuePatrick Georgi2023-10-1120-77/+1
| | | | | | | | | | | | | | | | | | We have a tiny HEAP_SIZE by default, except when we don't, and mainboards that override it, or not. Since memory isn't exactly at a premium these days, and unused heap doesn't cost anything extra, just crank it up to the highest value we have in the tree by default and remove all overrides. Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* memlayout.ld: Increase RAMSTAGE size to more than 1MB everywherePatrick Georgi2023-10-1118-22/+22
| | | | | | | | | | | | | This is in preparation of a larger heap. I went for 2MB because why not? Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/amd/genoa: Enable eSPI earlyArthur Heymans2023-10-106-0/+90
| | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/genoa: Add aoac.c & enable AOAC devices earlyArthur Heymans2023-10-105-0/+57
| | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic9553e6016c92c9b1678c395cd6a9e6860bf8a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76506 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/genoa: Enable cf9 IO earlyArthur Heymans2023-10-101-1/+1
| | | | | | | | | Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/brya/var/dochi: update gpio settingsMorris Hsu2023-10-102-0/+212
| | | | | | | | | | | | | | Configure GPIOs according to schematics revision 20230923. TEST=emerge-brya coreboot Change-Id: I10bd1b72c9b0299b8d29ab642fddb5f0c4727652 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
* mb/google/dedede: Wait for HPD on dibbi variantsReka Norman2023-10-106-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Type-C monitors do not immediately assert HPD. If we enter FSP-S before HDP is asserted, display initialisation may fail. So wait for HPD. This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP output on cold boots") on puff, except we don't use google_chromeec_wait_for_displayport() since that EC command was removed for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if HDMI is connected, which is the same behaviour as puff and fizz. TEST=On dibbi, connect a display via a Type-C to HDMI dongle and check the dev and recovery screens are now displayed correctly. Also check the logs in the following cases: Cold reboot in dev mode, Type-C to HDMI dongle: HPD ready after 800 ms Warm reboot in dev mode, Type-C to HDMI dongle: HPD ready after 0 ms Cold/warm reboot in dev mode, direct Type-C: HPD ready after 0 ms Cold/warm reboot in dev mode, direct HDMI: HPD ready after 0 ms Cold/warm reboot in dev mode, no display: HPD not ready after 3000 ms. Abort. Change-Id: Id4657b5d5a95a68ecbd9efcf3585cf96ad1e13e1 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* mb/google/rex/var/screebo: Update DTT settings for thermal controlKun Liu2023-10-101-10/+6
| | | | | | | | | | | | | | | | | | update DTT settings for thermal control, as follows: 1.Cancel TCPU trip point and fine tune other protection temperature on the Critical policy table 2.Fine tune EC/Bios protection temperature BUG=b:291217859 TEST=emerge-rex coreboot Change-Id: I0e2ff6eea9fed71ad7680c1fac4921984b87aca5 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78290 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex/var/rex0: update thermal settings to start fan earlierSumeet Pawnikar2023-10-101-14/+14
| | | | | | | | | | | | | | | | | | | Internal testing showed that CPU heatsink gets hot and temperature goes over 75C. In this situation, the fan does not even start to lower down CPU temperature. This is because of existing temperature thresholds of TSR0 and TSR1 sensors are set at 45C to start fan. With updated new settings based on tuning from thermal team, the fan starts early at 43C for TSR0 and TSR1 so the CPU temperature stays below 75C. BUG=b:302673874 TEST=Built and tested on google/rex board Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I6580652d6165946e98ecf1b46ace3352cd34dcdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* include/stddef: define SIZE_MAXPatrick Georgi2023-10-101-0/+1
| | | | | | | | | | | It's needed for future work. Change-Id: I3419d11072bc0e3791ad08144c2a25c607550f28 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* sb/intel/bd82x6x: Use helper for PCIe hotplugPatrick Rudolph2023-10-091-5/+9
| | | | | | | | | | | | | | | Introduce pci_is_hotplugable is helper to find hotpluggable PCIe devices. Test: PCI express slot is still marked as the only hotpluggable PCIe root port. Change-Id: I25aae540ff2ffa3ec5b93ed9caa838b4e50048d2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78227 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x: Disable unused PCIe root portsPatrick Rudolph2023-10-091-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow the PCH BIOS spec more closely by porting the broadwell and braswell PCIe downstream device detection. To safe power disable PCIe root ports that have no downstream device connected. By setting the FLAGS_SLOT bit in register PCI_EXP_FLAGS the PCI_EXP_SLTSTA_PDS bit will be updated with in band device detection from the PCIe PHY. While this is primarly used for PCIe hot-plug detection, it is more reliable than probing for downstream devices by reading DID/VID PCI registers. The FLAGS_SLOT bit should stay cleared for integrated devices, as those are known to be present, but to simplify the code all PCIe ports will have the FLAGS_SLOT bit set. There currently used devicetrees might also be lacking integrated devices on the PCH root ports... The SLOTCAP field must be updated by BIOS when the FLAGS_SLOT is set, but it shouldn't be filled for integrated devices. Until now the SLOTCAP field has always been populated and it never was a problem. - Set FLAGS_SLOT "Slot Implemented" bit early. - Read bit PCI_EXP_SLTSTA_PDS to detect connected downstream devices as done on braswell. - Disable unused PCIe slots that are not hotplugable. - Set BIT26 in register 0x338 and wait for bits in register 0x328 to clear as done on broadwell. Test: Tested on Lenovo X220. Unused root ports are disabled and port that are in used or marked hot-plug are kept enabled. Change-Id: I8ccfcab2e0e4faba8322755a4f8c2108d9b007ac Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78226 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: PCI: Fix translation windowJianjun Wang2023-10-091-18/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled. The root cause is using __fls() will get a smaller value when the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence the PCIe translation window size is set to 0x2000000. Accessing addresses higher than 0x2300000 will fail. Fix translation window by splitting the MMIO space to multiple tables if its size is not a power of 2. Resolves: https://ticket.coreboot.org/issues/508. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, it can boot with and without the CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option. BUS=b:298255933 BRANCH=cherry Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78044 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x: Follow PCH BIOS specPatrick Rudolph2023-10-092-1/+12
| | | | | | | | | | | | | | | PCH BIOS spec says that BIOS must clear BIT26 in register 0x338 in PEI, as done on lynxpoint. Copy and adapt the lynxpoint code to do the same on bd82x6x. Add special case for UM77 chipset, which only has 4 PCIe ports. Test: System still boots and all PCIe ports are fully working. Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* soc/amd/common/vboot: Fix PSP verstage timestamps after TSC adoptionKarthikeyan Ramasubramanian2023-10-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 26d54b70e282 ("soc/amd/common/cpu: use TSC_MONOTONIC_TIMER for SOC_AMD_COMMON_BLOCK_TSC") updated all the AMD SoCs with Zen-based CPU cores to use TSC_MONOTONIC_TIMER. The same change adjusted the PSP Verstage timestamps (in microseconds) to the x86 TSC rate. But it included only the base_time during the adjustment leaving the individual entry timestamp. This leads to incorrectly adjusted PSP Verstage timestamps. Fix the adjustment logic. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that the PSP Verstage timestamps in cbmem -t output are adjusted correctly. Before this change: 5:start of verified boot 67,890 (69,936) 503:starting to initialize TPM 67,890 (0) 504:finished TPM initialization 67,902 (12) 505:starting to verify keyblock/preamble (RSA) 67,906 (3) 506:finished verifying keyblock/preamble (RSA) 67,984 (77) 511:starting TPM PCR extend 67,984 (0) 512:finished TPM PCR extend 67,992 (7) 513:starting locking TPM 67,992 (0) 514:finished locking TPM 67,995 (3) 6:end of verified boot 67,995 (0) 11:start of bootblock 572,152 (504,156) After this change: 5:start of verified boot 71,000 (73,040) 503:starting to initialize TPM 71,065 (65) 504:finished TPM initialization 101,506 (30,441) 505:starting to verify keyblock/preamble (RSA) 110,624 (9,118) 506:finished verifying keyblock/preamble (RSA) 297,101 (186,477) 511:starting TPM PCR extend 297,297 (196) 512:finished TPM PCR extend 315,338 (18,041) 513:starting locking TPM 315,341 (3) 514:finished locking TPM 322,922 (7,581) 6:end of verified boot 322,943 (21) 11:start of bootblock 570,296 (247,353) Change-Id: I3e52bef22f65596152f29c511bed680427660ff5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78231 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/dedede: Create dexi variantKenneth Chan2023-10-0912-0/+509
| | | | | | | | | | | | | | | | Create the dexi variant of the taranza project by copying the files to a new directory named for the variant. BUG=b:303533815 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DEXI Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I708a16cb864dca7309cb0201e7887af7456a4885 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78249 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/joxer: Configure Acoustic noise mitigationMark Hsieh2023-10-091-0/+7
| | | | | | | | | | | | | | | - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:303533832 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I575da55b96bf4deacec5c0992eae9930eb0745d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* soc/intel/meteorlake: Reserve IOE P2SB MMIO correctlyKane Chen2023-10-091-2/+2
| | | | | | | | | | | | | | | | The original code only reserves IOM mmio, but there is other asl code that requires to program ioe p2sb mmio such as IOE PCIE clk request control. See \_SB.ECLK.CLKD in src/soc/intel/common/acpi/pcie_clk.asl TEST=as before: suspend_stress_test 50 cycle pass, type-c display OK on screebo Change-Id: Ie55f7975277b390f776e44596c42e426ba9cd235 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78252 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/nissa/var/joxer: Config I2C frequencyMark Hsieh2023-10-091-9/+9
| | | | | | | | | | | | | | | | | | | Measured the I2C frequency meets spec - I2C0 (TPM): 949.7 Khz - I2C1 (TouchScreen): 395.8 Khz - I2C3 (Audio): 387.4 Khz - I2C5 (Touchpad): 384.8 Khz BUG=b:303356736 TEST=USE="project_joxer emerge-nissa coreboot" and check all I2C devices measurement result Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I17dd1cb7800d00669f86fc6e2b350757695da881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78218 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/{rex,ovis}: Disable package C-state auto demotionSukumar Ghorai2023-10-074-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Package C-state auto demotion feature allows hardware to determine lower C-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter below PC8 state and additional power savings ~30mW in Local-Video-Playback scenario. BUG=b:303546334 TEST=Local build successfully & Boot to OS successfully - Also check platform enter PC8 state in local video playback - before this change: # iotools rdmsr 0 0xE2 -> 0x0000000060008008 - After # iotools rdmsr 0 0xE2 -> 0x0000000000008008 Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78250 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* device/pci_def.h: Add more bitsPatrick Rudolph2023-10-061-0/+5
| | | | | | | | | | | Add more fields for PCIe slots status and link control and slot capabilities. Change-Id: I64e40ea6bd731cd52ce006224b7c3091d5ef3aac Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* cpu/intel/model_206ax: Only use supported C-statesPatrick Rudolph2023-10-061-5/+59
| | | | | | | | | | | | | | | | | | | When advertising C-state using the ACPI _CST object, make sure to only advertise those that are supported by the CPU. Downgrade if it's not and make sure to not advertise duplicate states. Add debug prints for the finally selected mapping of ACPI C-state vs Intel CPU C-state. Test: Tested on Lenovo X220. All C-states are still advertised as all are supported. Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* cpu/intel/model_206ax: Use haswell cstate_mapPatrick Rudolph2023-10-062-50/+37
| | | | | | | | | | | | | | | Make the code look like on newer platforms. This doesn't change functionality. Test: Lenovo X220 still boots and advertises all C-states as before. Change-Id: Ie7076d11720d55a4ac11318cbbdab9f75d08e15e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78193 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cpu/intel/model_206ax: Print supported C-statesPatrick Rudolph2023-10-061-1/+21
| | | | | | | | | | | | | | | | According to the BWG C-states are processor specific and BIOS must check if a C-state is supported at all. Print the supported C-states in before ACPI _CNT generation. Test: Tested on Lenovo X220 using Intel i5-2540M. All C-states are reported as supported. Change-Id: I713712a1a104714cbf3091782e564e7e784cf21d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78133 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/cpu_common: Add cpu_get_c_substate_supportPatrick Rudolph2023-10-062-0/+29
| | | | | | | | | | | | | Add a function to get the number of substates supported by an Intel CPU C-state. Test: Can read out the supported C-state substates. Change-Id: Ie57e87609ea5d6ec6f37154e8b84f1e9574aa4a9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* cbfs: Restore 32-bit padding in cbfs_headerIvan Jager2023-10-061-1/+1
| | | | | | | | | | | | | | | | | | It was changed from a fixed size-1 array to a flexible array in commit 242bac0e162c ("…: Use C99 flexible arrays") which resulted in a change to the serialized format as the header size was no longer the same. That broke other tools that read CBFS files, like diffoscope https://github.com/NixOS/nixpkgs/issues/256896 Change-Id: I4199dcc4823469c5986ac967a55b1c85cc62f780 Signed-off-by: Ivan Jager <aij+git@mrph.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78239 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timingCong Yang2023-10-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | Based on the power sequence of the panel [1], the power on T3 sequence VSN to RESET should be larger than 1ms. Because the Power IC descending slope takes 2ms, actual measurement needs 3ms to meet the timing of panel sequence. [1] HX83102-J02_Datasheet_v03.pdf BUG=b:302212730 BRANCH=corsola TEST=emerge-staryu coreboot chromeos-bootimage and boot the panel Change-Id: I488c746d1fcfc165125b0ecccb0bccbb99231b00 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78185 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
* soc/intel: separate slp-s0 residency counter frequency in LPIT tableSukumar Ghorai2023-10-052-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Intel platforms use Low Power Idle Table (LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped IO Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC. Whereas slp_s0 residency counter running in different frequency. BUG=b:300440936 TEST=check kernel cpuidle sysfs are created after kernel boot cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* spi/winbond: Use spi_flash_bpbits in winbond_bpbits_to_regionDaniel Gröber2023-10-051-19/+58
| | | | | | | | | | | | This consolidates the bp, tb, cmp, srp0 and srp1 variables under the new spi_flash_bpbits struct to allow treating them as one unit in the refactoring to follow. Change-Id: I2a1a77fb73047df733498c0fa8b8de1153c3b09e Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42113 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi: Add new struct spi_flash_bpbits for block protection bitsDaniel Gröber2023-10-051-0/+11
| | | | | | | | | | | | | Currently the block protection bits are being passed around as individual arguments. We will use this new struct to replace the corresponding arguments in the winbond_bpbits_to_region and winbond_set_write_protection functions. Change-Id: I02828b1f764aea29374e794001e74cdc86a94c92 Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kBArthur Heymans2023-10-051-1/+1
| | | | | | | | | | | | This fixes building lenovo/x200 with VBOOT. All supported CPUs have enough L2 cache to support this. Change-Id: Ifd6a16ce36c86349955cd7b7ddb3f74a19c17c4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mb/google/nissa/var/quandiso: Change camera fw_config feildRobert Chen2023-10-051-5/+5
| | | | | | | | | | | | | | | Quandiso reserve bit 11 for mipi camera usage. BUG=b:300574047 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id4343083f0d69a49c642657d165ceac349cd7422 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78213 Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-26 11:14:53 +0000