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* nb/intel/x4x: Reset DQS probe on all channelsAngel Pons2021-01-151-5/+7
| | | | | | | | | | Eaglelake MRC 2.55 does this, and also stalls for less time. Change-Id: Iaaefd32c341a490e5c129df865407ec3f8da8212 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/pineview: Extract HPET setup and delay functionAngel Pons2021-01-157-50/+62
| | | | | | | | | | | | | To allow other platforms to reuse this code, extract it into a separate compilation unit. Since HPET is enabled through the southbridge, place the code in the southbridge scope. Finally, select the newly-added Kconfig option from i82801gx and replace lpc.c `enable_hpet` function. Change-Id: I7a28cc4d12c6d79cd8ec45dfc8100f15e6eac303 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* vc/eltan/security/verified_boot/vboot_check.c: Add check PROG_POSTCARFrans Hendriks2021-01-151-1/+6
| | | | | | | | | | | | | | | | | On Coffee Lake systems prog_locate_hook() is called with PROG_POSTCAR. For this reason the early check is not executed. Add check for prog->type == PROG_POSTCAR, but execute verified_boot_early_check() once. BUG = N/A TEST = Build and boot on Facebook FBG1701 and Intel CoffeeLake system Change-Id: Ia3bd36064bcc8176302834c1e46a225937d61c20 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48852 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/facebook/fbg1701/Kconfig: Remove dependency for USE_VENDORCODE_ELTANFrans Hendriks2021-01-151-1/+0
| | | | | | | | | | | | | | | make olddefconfig on other projects using USE_VENDORCODE_ELTAN results in error. USE_VENDORCODE_ELTAN unmet direct dependencies. Remove dependency on VBOOT for USE_VENDORCODE_ELTAN. TEST = Build and boot on Facebook FBG1701 Change-Id: I5881c334955c73ae0f1a693f95ceb1aee62ee898 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
* mb/google/asurada: Implement HW reset functionYidi Lin2021-01-151-0/+4
| | | | | | | | | | TEST=call do_board_reset() manually. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I355f71e731f1045cd80a133cd31cf4d55f14d91f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/amd/cezanne,picasso/uart: remove unneeded struct nameFelix Held2021-01-152-2/+2
| | | | | | | | | | | | | This struct isn't used anywhere else, so there's no need to name it. Change-Id: I22eda07f14096d2b7400e6ab715641ffd68fbc08 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49444 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/volteer: Configure UsbTcPortEn valueBrandon Breitenstein2021-01-141-8/+1
| | | | | | | | | | | | | | | | | | | | | | The default value is not sufficient to correctly configure the Type-C ports as it has all ports disabled by default. On Volteer ports 0 and 1 are enabled so setting this value to 0x3 and correctly keeping the IomPortPadCfg values at 0 for ports that have a retimer and ports that are not configured. These values were set to 0x90000000 to avoid s0ix issues which arose from the UsbTcPortEn value being incorrect. BUG=b:159151238 BRANCH=firmware-volteer-13672.B TEST=Built image for Voxel and verified that s0ix cycles complete without any issues Change-Id: Ib4f2bd0f68debd4e97ccaab9e1d8a873dc4e4d9f Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48814 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tgl: Add configurable value for UsbTcPortEnBrandon Breitenstein2021-01-142-0/+8
| | | | | | | | | | | | | | | | | | | As a requirement of TCSS this setting needs to be correctly set to determine what Type-C ports are enabled on the platform. Without this value correctly set there can be adverse effects on the other TCSS specific values. BUG=b:159151238 BRANCH=firmware-volteer-13672.B TEST=Built image for Voxel and verified that S0ix cycles no longer fail when the IomPortPad is set to 0 Change-Id: I6c5260cda71041439fe89d15bd3cafd4052ef1e7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* soc/amd/picasso: Remove printf in aslRaul E Rangel2021-01-142-26/+0
| | | | | | | | | | | | | | | | These are no longer really useful. We can also enable Power Resource ACPI debug in the kernel if we want these messages. BUG=none BRANCH=zork TEST=emerge-zork and verify debug messages are no longer posted Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I936e816266825f1c59377c2e079ffe1a5188838c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* build system: Structure and serialize INTERMEDIATEPatrick Georgi2021-01-1410-44/+14
| | | | | | | | | | | | | | | | | | | | | | | Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/uart: add missing device/device.h includeFelix Held2021-01-141-0/+1
| | | | | | | | | Change-Id: Ie3188d36e8ecacab42818c8619122751fcb7cdf8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49379 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: add remaining non-ACPI parts of UART supportFelix Held2021-01-141-0/+35
| | | | | | | | | | | | | | | | The ACPI part still needs some more code to be in place, so add that later. TEST=Together with the currently not merged rest of the amdfw patch train applied this results in working serial console in bootblock in Majolica. Change-Id: Ia844e86a80c19026ac5b47a5a1e91c2553ea5cca Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49378 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: add AOAC supportFelix Held2021-01-145-1/+77
| | | | | | | | | Change-Id: I9d7574b60640eaf9a47a797e823324edeaf1e770 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* mb/amd/majolica: use integrated UART as consoleFelix Held2021-01-141-0/+1
| | | | | | | | | Change-Id: Ic6dcbe999234f233fbac8fbdb06d22c8577b1a40 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/cezanne: add console UART supportFelix Held2021-01-147-0/+87
| | | | | | | | Change-Id: I1a01cc745c7049dc672bca12df5c6b764ac9b907 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UARTFelix Held2021-01-145-28/+11
| | | | | | | | | | | | | | | Since the functions that get called by the coreboot console initialization code aren't in the SOC-specific code anymore, the SOC's uart.c can be included unconditionally in the build now. This also replaces the STONEYRIDGE_UART Kconfig option with the common AMD_SOC_CONSOLE_UART one. Change-Id: I09c15566a402895d6388715e8e5a802dc3c94fdd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49375 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/uart/Makefile: use all targetFelix Held2021-01-141-7/+1
| | | | | | | | | Change-Id: I5079decfae982d2222bb9a7f5155d51885d4d3a9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49374 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/piasso/uart: move get_uart_base prototype to common code headerFelix Held2021-01-144-3/+12
| | | | | | | | | | | | This will result in less code duplication when the common AMD SoC UART support gets used for more AMD SoCs. Change-Id: Id1786f32324de3e3947d792c599e2019705c5a85 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49373 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/uart: move CONSOLE_UART_BASE_ADDRESS back to SoC codeFelix Held2021-01-142-14/+8
| | | | | | | | | | | | | | | This partially reverts commit 6f8f9c969be9d471464f1b6a42b4bb1c2590db5c by moving CONSOLE_UART_BASE_ADDRESS back to the SoC-specific code, since the number and base addresses of UARTs turned out to be rather SoC- specific. The help text for the AMD_SOC_CONSOLE_UART option also contained those base addresses, so remove that as well. Change-Id: I01211ec62421c56f22ed611313d6245a05bdea67 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49372 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: remove broken and unused legacy UART supportFelix Held2021-01-144-99/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UARTs in the Picasso SoC are memory mapped, but there is also some hardware support that isn't used by any board to make the UARTs behave like the ones found on legacy x86 machines from the 90s. In the MMIO mode the MMIO address of the UART controller is passed to the OS via ACPI. The OS expects the base clock of the UART controller to be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It is also possible to enable additional decodes from four 8 byte legacy I/O locations used for serial ports to the different UART controllers, which doesn't disable the MMIO access though. The legacy I/O-mapped serial ports are usually expected to have a base clock of 16*115200Hz which the hardware can also provide to the UART's baud rate generator. So there are two possible valid configurations to use the UARTs; either MMIO access in combination with a 48MHz base clock or the legacy I/O decode with a ~1.8MHz base clock. The existing code unconditionally generates ACPI objects for all enabled UARTs, so those shouldn't be put into legacy mode and switching the base clock to ~1.8MHz was only done in the case that the UART was used as coreboot console UART which still used the MMIO access, but the lower base clock. Since no board even selects this option and it's rather invasive to properly implement this feature, just drop the corresponding broken code. TEST=SoC UART console still works on Mandolin. Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/boten: Support ELAN i2c-hid touchscreen for botenflexStanley Wu2021-01-141-0/+20
| | | | | | | | | | | | | | Update ELAN i2c-hid touchscreen configuration BUG=b:172517685 BRANCH=dedede TEST=Verify touchscreen is working fine on botenflex Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Ia7c81fd0a772968ec32406f1e366a90481fc5ad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/picasso: Disable CBFS MCACHERaul E Rangel2021-01-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This is causing boot errors on zork: coreboot-v1.9308_26_0.0.22-18590-g4598a7bed945 Wed Dec 16 17:32:25 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00820f01 PSP boot mode: Development Silicon level: Pre-Production PMxC0 STATUS: 0x800 BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area FW_MAIN_B found @ 312000 (3137280 bytes) ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106 BUG=b:177323348 TEST=Boot ezkinil to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1f2bbdd9c87c4efdfb0042e90a20b489fa0efced Reviewed-on: https://review.coreboot.org/c/coreboot/+/49128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* sb/intel: Add CBMC entries in GNVSKyösti Mälkki2021-01-1310-5/+20
| | | | | | | | | | | While unused, this allows use of a common initialisation code for GNVS allocation. Change-Id: Ie84b5a3e16d3baa12bcd5dadac0b1f7edb323272 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86/smm: Pass GNVS with smm_module_loader v2Kyösti Mälkki2021-01-131-0/+2
| | | | | | | | | Change-Id: I9971069803a7cd1b9be0ac0cfa410b6e1fdc3eeb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ACPI: Have single call-site for acpi_inject_nvsa()Kyösti Mälkki2021-01-1322-102/+4
| | | | | | | | | Change-Id: I61a9b07ec3fdaeef0622df82e106405f01e89a9e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48719 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kahlee,zork: Use mainboard_fill_gnvs()Kyösti Mälkki2021-01-134-28/+24
| | | | | | | | Change-Id: Ic9cdcc497bf1a9f5bfed5e6d95040bfa602b0b89 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48732 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ACPI: Add common acpi_fill_gnvs()Kyösti Mälkki2021-01-1317-87/+14
| | | | | | | | | Change-Id: I515e830808a95eee3ce72b16fd26da6ec79dac85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48718 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd: Rename to soc_fill_gnvs()Kyösti Mälkki2021-01-133-30/+13
| | | | | | | | | | | | Replace acpi_create_gnvs() under soc/ to reflect their changed functionality. Change-Id: I61010f64a4a935f238e6dcd0f8c1340a6cc68eb4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd: Rename to pm_fill_gnvs()Kyösti Mälkki2021-01-134-13/+9
| | | | | | | | | Change-Id: I80f92bed737904e6ffc858b45459405fe76f1d04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/volteer/variants/delbin: Update PL1 min and max for DelbinDeepika Punyamurtula2021-01-131-5/+5
| | | | | | | | | | | | | | | Update PL1 min and max values for Delbin systems BUG=b:168958222 BRANCH=None TEST=Build and verify on delbin system Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: I2152f0dbeb0ae463b78464571b6c434830f0082a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
* sb/intel/bd82x6x: Correct xHCI sleep workaroundAngel Pons2021-01-132-43/+77
| | | | | | | | | | | | | | | | The S3/S4 workaround is specific to Panther Point stepping A0, and it is wrongly implemented. Rewrite the whole function as per reference code. Since this runs in SMM, be overly cautious and double-check everything. Do not rely on GNVS to determine if xHCI is enabled. Instead, check whether the corresponding bit in the Function Disable register is set. Only Panther Point has xHCI, so exit early if this is not the case. Change-Id: Iabce6c52fac781dc694f5b589fab2e9fe438f3f5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer: Add CSE Lite SKU support to Copanohao_chou2021-01-131-0/+1
| | | | | | | | | | | | | | | This will allow CSE RW FW updates and also fixes the problem where no sound is emitted from the speakers. BUG=b:174338903 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I875f6b32c4053ef6d23ad7606cd35a129a78c306 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49290 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Disable TC cold supportSrinidhi N Kaushik2021-01-131-0/+3
| | | | | | | | | | | | | | | | | | This change lets IOM consider all USB connected devices as device attached(DA) scenario. While connecting a typec-to-a dongle, IOM would disable TC cold and help to resolve enemuration failure after usb3 device is plugged into the dongle. BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/49244 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: rename uart_max_indexMichael Niewöhner2021-01-129-10/+10
| | | | | | | | | | | | | | | The name `..._index` is confusing since the maximum index of an array is not `ARRAY_SIZE(array)` but `ARRAY_SIZE(array) - 1`. Rename `uart_max_index` to `uart_ctrlr_config_size` to make the name match the variable´s value. Change-Id: I7409c9dc040c3c6ad718abc96f268c187d50d79c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/brya: Initialize overridetree.cbEric Lai2021-01-122-0/+300
| | | | | | | | | | | | | Initiate overridetree.cb based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I31e5ac1703476083ac71dac30b0a3299b38384c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Add gpio tableEric Lai2021-01-121-2/+371
| | | | | | | | | | | | | Follow latest schematic to fill gpio table. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3a983605b5139ff8510a0cf225e6564b9215cb1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer: Configure Voxel USB2 ports for Type CJohn Zhao2021-01-121-0/+3
| | | | | | | | | | | | | | | | | | | | | Two USB2 ports 4 and 9 are assigned to type C connectors on Voxel board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Booted to kernel on Voxel board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia370a449a41701e690c1c507d70bedfce2076a65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE`Angel Pons2021-01-122-2/+1
| | | | | | | | | | It is only used in one place, and there's two other equivalent macros. Change-Id: I7c8241e28f688abd2df8180559dd02ee441c7023 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/x86/sipi_vector: Simplify loop getting unique CPU numberPatrick Rudolph2021-01-121-3/+2
| | | | | | | | | | | | Get rid of using eax and reload counter on race condition. Change-Id: Ie4b9957d8aa1f272ff1db5caf2c69d1e1f086a03 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47714 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/pci_device.c: Use same indents for switch/caseFelix Singer2021-01-121-1/+1
| | | | | | | | | | Use same indents for switch/case to fix linter issues. Change-Id: I5c6abf5b918bac3df8d7617824392f2ec932cb32 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/common/pcie: Add helper function for getting mask of enabled portsFurquan Shaikh2021-01-123-0/+58
| | | | | | | | | | | | | | | | | | This change adds a helper function `pcie_rp_enable_mask()` that returns a 32-bit mask indicating the status (enabled/disabled) of PCIe root ports (in the groups table) as configured by the mainboard in the device tree. With this helper function, SoC chip config does not need to add another `PcieRpEnable[]` config to identify what root ports are enabled. Change-Id: I7ce5fca1c662064fd21f0961dac13cda1fa2ca44 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48968 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Use __pci_0_00_0_config in config_of_soc()Furquan Shaikh2021-01-121-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change updates the definition of config_of_soc() to a macro that expands to __pci_0_00_0_config instead of accessing the config structure by referencing the struct device. This allows linker to optimize out unused portions of the device tree from early stages. With this change, bootblock .text section size drops as follows: Platform | Size without change | Size with change | Reduction | ---------------|---------------------|------------------|-------------| GLK (ampton) | 27112 bytes | 9832 bytes | 17280 bytes | APL (reef) | 26488 bytes | 17528 bytes | 8960 bytes | TGL (volteer2) | 47760 bytes | 21648 bytes | 26112 bytes | CML (hatch) | 40616 bytes | 22792 bytes | 17824 bytes | JSL (waddledee)| 37872 bytes | 19408 bytes | 18464 bytes | KBL (soraka) | 31840 bytes | 21568 bytes | 10272 bytes | As static.h is now included in device.h which gets pulled in during the unit tests, a dummy static.h is added under tests/include. Change-Id: I1fbf5b9817065e967e46188739978a1cc96c2c7e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/alderlake: Add PCH ID 0x5182Subrata Banik2021-01-123-1/+4
| | | | | | | | | | | TEST=Able to build and boot ADLRVP. Change-Id: Ia331998b46abcf10e939078dea992589f09139bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49301 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/genesyslogic/gl9763e: Add HS400ES compatibility settingsBen Chuang2021-01-122-0/+9
| | | | | | | | | | | | | By default, the HS400 mode of GL9763E is slow mode (150MHz). Therefore, the slow mode is disabled for HS400 running at 200MHz. For eMMCs such as Hynix (H26M74002HMR) on HS400, adjust the internal Rx latch dealy of HS400 to have better compatibility. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Change-Id: I84844c2432d4223d9929182c5c430915e52875b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/zork/var/vilboz: Fix FW_CONFIG_SHIFT_WWAN valueJohn Su2021-01-121-1/+1
| | | | | | | | | | | | | | | | | | The FW config takes 2 bits for USE_FAN[27,28]. So FW_CONFIG_SHIFT_WWAN value should be 29. BUG=b:174121847 BRANCH=zork TEST=build vilboz Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ica6d04f9c48aa0800189283608bf57416ac75cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49236 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/haswell: Add delay for TPM before Flex Ratio rebootAngel Pons2021-01-111-0/+5
| | | | | | | | | | | | | Commit 542307b815 (broadwell: Add small delay before Flex Ratio reboot) introduced a workaround for Broadwell. Implement it on Haswell as well. Since this is only necessary when a TPM is present on a system, only do the delay (which is not that small, to be honest) on TPM-enabled builds. Change-Id: Id8b58e9fa2a1c81989305f5b4b765b82c01e1596 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46941 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/haswell: Allow tuning VR for C-state operationsAngel Pons2021-01-112-2/+50
| | | | | | | | | | | Apply commit ff0f460e76 (broadwell: Add configuration for tuning VR for C-state operations) to Haswell, in preparation for unification. Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46920 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/haswell: Raise PSI1 threshold to 20AAngel Pons2021-01-111-1/+1
| | | | | | | | | | Haswell reference code version 1.9.0 uses the same value as Broadwell. Change-Id: I979ea1b4ba2962bd0c55cfb9d0c291f32cf5fcad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46919 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/haswell: Enable turbo ratio if availableAngel Pons2021-01-111-4/+7
| | | | | | | | | | | Commit 7f28e4ee01 (broadwell: Enable turbo ratio if available) is also applicable to Haswell, since the MSR definitions are the same for both. Change-Id: Ic5f30a5b06301449253bbfb9ed58c6b35a767763 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46918 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSRAngel Pons2021-01-111-6/+0
| | | | | | | | | | | The MSR only needs to be set when IO MWAIT redirection is to be enabled. This was copied from Sandy Bridge, which already had this inconsistency. Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46917 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 11:47:37 +0000