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* drivers/spi: ignore -Wvla on clang tooGreg V2019-10-091-1/+1
| | | | | | | | | Change-Id: I99bc6877680b32f2bae78437ab0482baa65496d8 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* acpi_table_header: Replace hard-coded length via sizeof(acpi_fadt_t)Himanshu Sahdev2019-10-095-5/+5
| | | | | | | | | | | Minimize use of hard-coded value for acpi_table_header->length to soft code. Replace length of acpi_header_t with sizeof(acpi_fadt_t). Change-Id: Ibcae72e8f02497719fcd3f180838557e8e9abd38 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* mb/google/hatch: Set FPS as wake sourceShelley Chen2019-10-095-5/+9
| | | | | | | | | | | | | | BUG=b:142131099 BRANCH=None TEST=powerd_dbus_suspend, ensure DUT in S0ix touch fp sensor and ensure DUT wakes up in S0 Change-Id: If57094aa1076d79ac0886b71fa5532411bfeb45f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* SMBIOS (Type 17): Add HBM device type and DIE form factor valueElyes HAOUAS2019-10-091-0/+3
| | | | | | | | | | | Add High Bandwidth Memory, High Bandwidth Memory Generation 2 and new form factor value (Die). Change-Id: Ia174e09bffdadeed4a18d443f75e2386d756e9bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35893 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* SMBIOS: (Type 9) Add PCI Express Gen 4 valuesElyes HAOUAS2019-10-091-1/+7
| | | | | | | | Change-Id: I616a435d80715bee6f7530d7318319556a7580e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* superio/it8772f: use pnp_ops.h for pnp register accessFelix Held2019-10-082-39/+17
| | | | | | | | Change-Id: I983249fb54b6fbccc4339c955cb5041848b21cf8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* superio/winbond/w83627*: use hwm5_conf.h for HWM setupFelix Held2019-10-082-8/+8
| | | | | | | | Change-Id: Id78042606f02e02035dc917d162d0c98c9de38a4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* intel/dcp847ske: use functions from hwm5_conf.h for HWM setupFelix Held2019-10-081-6/+2
| | | | | | | | Change-Id: I67de5260a756fc7b1cf0ec1903bee0058a2dcb06 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* superio/it8772f: use HWM access functionality from hwm5_conf.hFelix Held2019-10-081-35/+26
| | | | | | | | Change-Id: I12ac8dd0503f3c46fdb50e49df60c01387128b55 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* superio/hwm5_conf: factor out HWM access from ITE env_ctrlFelix Held2019-10-082-71/+109
| | | | | | | | | | | | | Nuvoton and Winbond use the same off-by-5 indirect address space to access their hardware monitor/environment controller in the SIO chip, so move this to a common location and replace the inb/outb calls with the corresponding inline functions from device/pnp.h Change-Id: I20606313d0cc9cf74be7dca30bc4550059125fe1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* asus/f2a85m_pro: Fix superio type in devicetreeKyösti Mälkki2019-10-081-1/+1
| | | | | | | | | | | The superio driver that was linked in is nct6779d but static devicetree expected symbol superio_nuvoton_nct5572d_ops. Change-Id: I648b7680bb39b9ff5b38cc3bd5147bd336e0b282 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* device: Use scan_static_bus() over scan_lpc_bus()Nico Huber2019-10-0833-41/+31
| | | | | | | | | | | | | | Devices behind LPC can expose more buses (e.g. I2C on a super-i/o). So we should scan buses on LPC devices, too. Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/root_device: Consolidate common _scan_bus() functionsNico Huber2019-10-086-26/+14
| | | | | | | | | | | scan_usb_bus() and root_dev_scan_bus() had the very same implementation. So rename the latter to scan_static_bus() and use that for both cases. Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31901 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Don't allow separate verstage to boot from romcc bootblockArthur Heymans2019-10-081-5/+0
| | | | | | | | | | | | | CONFIG_VBOOT_SEPARATE_VERSTAGE has a dependency on C_ENVIRONMENT_BOOTBLOCK so Kconfig already guards against this. Change-Id: I8f963a27f9023fd4c6ebc418059d57e00e4dfb4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35824 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Add a choice for selecting normal/fallback cbfs prefixArthur Heymans2019-10-081-2/+19
| | | | | | | | | | | | Setting the cbfs prefix is prone to error. Therefore add a Kconfig choice for 2 common values, fallback and normal, while still keeping the ability to specify an arbitrary value. Change-Id: I04222120bd1241c3b0996afa27dcc35ac42fbbc8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device/dram/ddr4: Check spd_bytes_total and spd_bytes_used valuesElyes HAOUAS2019-10-081-2/+16
| | | | | | | | | | | | | The value stored to 'spd_bytes_total' is never read. Now it is fixed. This is spotted using clang-tool v9. Also add a check if spd_bytes_used and/or spd_bytes_total are reserved and make sure that spd_bytes_used is not greater than spd_bytes_total. Change-Id: I426a7e64cc4c0bcced91d03387e02c8d965a21dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/lenovo/t60: Switch to override treePeter Lemenkov2019-10-085-257/+135
| | | | | | | | | Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34779 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/{t60,z61t}: Convert to variant boardPeter Lemenkov2019-10-0834-1627/+28
| | | | | | | | Change-Id: I0a3076780ac5cf183235f06e4c56d0707bf5e6ca Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* device/mmio.h: Add more bit field helpersHung-Te Lin2019-10-081-1/+7
| | | | | | | | | | | | | For fields with single bit, it's easier to declare as DEFINE_BIT(name, bit) Change-Id: If20e6b1809073b2c0dc84190edc25b207bf332b7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/drallion: Add detect pin for Wacom touchscreenFrank Wu2019-10-081-0/+2
| | | | | | | | | | | | | | Add the missing detect pin to fix Wacom touchscreen function. BUG=b:140415892,b:138082886 BRANCH=N/A TEST=N/A Change-Id: I8a1b48d4d502945b88e38393383512d30b684fa4 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35790 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kohaku: Assign GPP_A19 as reset_gpio of stylusSeunghwan Kim2019-10-082-7/+5
| | | | | | | | | | | | | | | | | Applying reset_gpio config of stylus for kohaku. GPP_A19 has been assigned in the latest schematics. We would keep GPP_A10 as output high for old revision devices temporarily. BUG=b:141914474 BRANCH=none TEST=verified stylus works internally Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I61f0f9a4378f47bf455f0726d44beeaf2f67197b Reviewed-on: https://review.coreboot.org/c/coreboot/+/35748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* mb/google/hatch: Preserve MRC training data across FW updateShelley Chen2019-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | Add PRESERVE to UNIFIED_MRC_CACHE so that we don't retain the memory training data upon a FW update unless we need to. We have had users complaining that a 15 second memory training upon update makes them believe that their device is not booting, thus many of them hard resetting before bootup. BUG=b:142084637 BRANCH=None TEST=flash RW_SECTION_A, RW_SECTION_B, and WP_RO sections and make sure memory training doesn't occur on following bootup. Change-Id: Ia5eb228b1f665a8371982544723dab3dfc40d401 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35803 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/octopus/variants/fleex: Adjust I2C0 CLK to meet specJohn Su2019-10-071-0/+2
| | | | | | | | | | | | | | | | | | After adjustment on Grob360S I2C0 CLK: 389.9 KHz BUG=b:141729962 BRANCH=master TEST=emerge-octopus coreboot chromeos-bootimage measure by scope with Grob360S. Change-Id: I6a30257b7978cc8899a55f9fd6ffffe01cb2a851 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* src: Capitalize Super I/OElyes HAOUAS2019-10-075-8/+8
| | | | | | | | Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* device: Rename scan_static_bus() -> enable_static_devices()Nico Huber2019-10-075-9/+9
| | | | | | | | | | | | | The new name should reflect better what this function does, as that is only one specific step of the scanning. Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/nm10: Fix enabling HPETArthur Heymans2019-10-062-2/+8
| | | | | | | | | | | | | | | | RCBA_HPTC needs to be read back to consistently enable HPET. This ought to fix raminit failing sometimes and SeaBIOS endlessly waiting for user input. TESTED on Intel D510MO, Fixes SeaBIOS waiting for input, without a timeout. Change-Id: I20a25fd97cd09fedb70469262c64d8d3828bb684 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35758 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/ocp/monolake: Add GPIO table to initialize custom configsJingle Hsu2019-10-061-0/+162
| | | | | | | | | | | | | | Add a GPIO table for Monolake to initialize GPIOs with custom board configurations. Tested on Monolake. Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* device/pci: Enable full 16-bit VGA port i/o decodingNico Huber2019-10-064-1/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So, the PCI to PCI bridge specification had a pitfall for us: Originally, when decoding i/o ports for legacy VGA cycles, bridges should only consider the 10 least significant bits of the port address. This means all VGA registers were aliased every 1024 ports! e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. However, it seems, we never reserved the aliased ports, resulting in silent conflicts we preallocated resources. We neither use much external VGA nor many i/o ports these days, so nobody noticed. To avoid this mess, a bridge control bit (VGA16) was introduced in 2003 to enable decoding of 16-bit port addresses. As older systems seem rather safe and well tested, and newer systems should support this bit, we'll use it if possible and only warn if not. With old (AGP era) hardware one will likely encounter a warning like this: found VGA at PCI: 06:00.0 A bridge on the path doesn't support 16-bit VGA decoding! This is not generally fatal, but makes unnoticed resource conflicts more likely. Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35516 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/model_2065x/bootblock: Remove dead codeArthur Heymans2019-10-061-52/+0
| | | | | | | | | | | | | This codepath is never takes as it checks if the CPU is at least ivybridge. Change-Id: Id064385f0c8bb0b094714129df6d8ba36c87a307 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/{lenovo/x201,packardbell/ms2290}: Remove unused ACPI symbolsArthur Heymans2019-10-062-8/+0
| | | | | | | | | Change-Id: I3a3174cf20cea60d8b2c4d0311a48ce9ffe1a8a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nb/intel/nehalem: Don't run graphic init on S3 resumeArthur Heymans2019-10-061-1/+2
| | | | | | | | | | | | | | | | The assumption is made that an ACPI aware an OS does not rely on firmware to initialize the display. TESTED on a Lenovo Thinkpad X201 with Linux 5.2, display still works after S3, more than 200ms in time saved (dropped from 411ms to 182ms in total in one test). Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* nb/intel/nehalem: Move PCH init to sb/intel/ibexpeakArthur Heymans2019-10-067-83/+98
| | | | | | | | | | | | | | | | | | | | This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock. Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* nb/intel/nehalem: Move romstage boilerplate to a common locationArthur Heymans2019-10-066-202/+147
| | | | | | | | | | | Move the mainboard_romstage_entry to a common location and provide mainboard specific callbacks. Change-Id: Ia827053617cead5d2cf8e9f06cb68c2cbb668ca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nb/intel/nehalem: Don't link walkcbfs.S in romstageArthur Heymans2019-10-061-1/+0
| | | | | | | | | | Change-Id: I5bb0c38353d340cc5d356fba299a4460e3f5bddc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35770 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/ibexpeak: Don't clear PMBASE regs in romstageArthur Heymans2019-10-062-66/+0
| | | | | | | | | | X201 boots fine without it. Change-Id: I20a8e598b07bf0a059dcb47651d1a26456863673 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35769 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/ibexpeak: Implement USB current settingsArthur Heymans2019-10-065-47/+165
| | | | | | | | | | | | | | | | This is based on the sandybridge settings. The current lookup table comes from the x201 vendor lookup table. Tested: USB mouse and webcam still work and current registers are the same as before. USB IR are not but the code follows EDS instead of the register replay. Change-Id: Icea9673623a62e7039d5700100a2ee238478abd1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35762 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/ibexpeak boards: Remove undocumented reset defaults from RCBA replayArthur Heymans2019-10-062-38/+0
| | | | | | | | | | | | The values read back in those ranges are identical before and after this change and the Lenovo Thinkpad X201 still boots fine. Change-Id: I406510e0573ac97003da7d97181abdfbfd2a872f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35760 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/ibexpeak boards: Remove handled RCBA entries from replayArthur Heymans2019-10-062-36/+20
| | | | | | | | | | | | | | The RCBA registers 0x3400-0x3500 are all handled elsewhere in the code, so no need to have a 'replay' of those. The remainder now consist of USB setup and undocumented bits that should likely not be touched at all. Change-Id: I69fc8a5e16f7cf0e1068d0d2ed678a6c2f6e70a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/intel/ibexpeak: Fix enabling HPETArthur Heymans2019-10-061-0/+1
| | | | | | | | | | | | | | RCBA_HPTC needs to be read back to properly work. This fixes SeaBIOS endlessly waiting for input instead of booting the default entry. Linux already fixes this itself. Change-Id: I22b8b34924f2add2185ec46470c1559bf2fb6d58 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35757 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/ibexpeak: Implement PCH function disable in chip_opsArthur Heymans2019-10-067-33/+140
| | | | | | | | | | | | | | | | This does the following: - implement a PCH disable function that will be called by the PCI drivers as part of their chip_ops - removes the iobp_x calls as those don't exist on ibexpeak - complete the devicetree with to be disabled PCI devices for the chip_ops to be called - Clean up some code copied from bd82x6x Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nb/intel/nehalem: Remove bogus GT PM initArthur Heymans2019-10-061-430/+3
| | | | | | | | | | | | | This was simply copied from sandybridge/gma.c. All these registers read back 0xffffffff or 0 or don't respond to reads. Change-Id: I094e7caa889a3175477aa78b91545ca804d423c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35746 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/nehalem: Disable PEG and IGD based on devicetreeArthur Heymans2019-10-064-3/+26
| | | | | | | | | | Tested on Thinkpad X201: PEG device hidden. Change-Id: Ib378458a55e18cc02fc49b3e6d6939d31dd4aa65 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35744 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/nehalem: Remove bogus MCHBAR writesArthur Heymans2019-10-062-51/+0
| | | | | | | | | | | On these CPUs the MCHBAR window is 16KiB large. This code was just copied from SNB. Change-Id: I263cfc678a2eb8eeee8ab9157c749359064a9be8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/intel/ibexpeak: Add CIR initializationArthur Heymans2019-10-065-34/+120
| | | | | | | | | | | | | | | | | This properly sets up the chipset initialization registers, instead of replaying an RCBA dump. The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI. TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3. Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* intel/fsp_broadwell_de: Rename from xx_DEV_FUNCKyösti Mälkki2019-10-063-24/+5
| | | | | | | | | | | | | | Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: I1a8675a4e613a8efc135b05cde36f166acaa7ed4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* soc/intel/common/block/p2sb/p2sb: Add missing PCI IDsPatrick Rudolph2019-10-052-0/+8
| | | | | | | | | | | | | | | The code is compiled on SKL/KBL, but the P2SB PCI IDs were missing. Add them to make sure that the BAR0 doesn't change when running PCI resource allocation. Change-Id: I7cffbbc7d15dad14cccd122a081099b51dc1ce07 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* kontron/986lcd-m,roda/rk886ex: Drop secondary PCI resetKyösti Mälkki2019-10-054-17/+0
| | | | | | | | | | | The extra PCI bus RST# and 200ms delay there was workaround for custom add-on hardware. Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* intel/i945,i82801gx: Refactor early PCI bridge resetKyösti Mälkki2019-10-055-35/+26
| | | | | | | | Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/fsp_baytrail: Define PCH_DEV_SLOT_I2C1Kyösti Mälkki2019-10-052-3/+5
| | | | | | | | Change-Id: I02c08b847fa1523e3296bdf9e3db5a7a322df72e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* intel/fsp_baytrail: Rename from xx_DEV_FUNCKyösti Mälkki2019-10-054-65/+63
| | | | | | | | | | | | | Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-09 19:18:39 +0000