| Commit message (Expand) | Author | Age | Files | Lines |
* | mainboard/bap/ode_e20XX: Change PCIe lines | Fabian Kunkel | 2016-07-31 | 2 | -16/+6 |
* | superio/nuvoton: Add Nuvoton NCT6791D | Omar Pakker | 2016-07-31 | 5 | -0/+181 |
* | src/vboot: Capitalize RAM and CPU | Elyes HAOUAS | 2016-07-31 | 2 | -3/+3 |
* | src/lib: Capitalize ROM, RAM, NVRAM and CPU | Elyes HAOUAS | 2016-07-31 | 4 | -4/+4 |
* | src/drivers: Capitalize CPU, RAM and ACPI | Elyes HAOUAS | 2016-07-31 | 7 | -8/+8 |
* | src/soc: Capitalize CPU, ACPI, RAM and ROM | Elyes HAOUAS | 2016-07-31 | 41 | -54/+54 |
* | src/acpi: Capitalize ACPI and SATA | Elyes HAOUAS | 2016-07-31 | 1 | -1/+1 |
* | sunw/ultra40m2: Fix handling non-existence of a device | Patrick Georgi | 2016-07-31 | 1 | -1/+3 |
* | sis/sis966: fix typo | Patrick Georgi | 2016-07-31 | 1 | -1/+1 |
* | sis/sis966: don't store a 32bit value in a 16bit variable | Patrick Georgi | 2016-07-31 | 1 | -3/+3 |
* | intel/broadwell: fix typo | Patrick Georgi | 2016-07-31 | 1 | -1/+1 |
* | intel/skylake: Enable signalling of error condition | Patrick Georgi | 2016-07-31 | 1 | -2/+2 |
* | google/reef: Update chromeos.fmd RO_SECTION | Furquan Shaikh | 2016-07-31 | 1 | -10/+10 |
* | intel/amenia: Enable DPTF in mainboard | Shaunak Saha | 2016-07-31 | 3 | -0/+102 |
* | google/reef: Enable DPTF in mainboard | Shaunak Saha | 2016-07-31 | 3 | -0/+102 |
* | gigabyte/ga_2761gxdk: Remove comment *endif* | Paul Menzel | 2016-07-31 | 1 | -1/+1 |
* | mainboard: Format irq_tables.c | Paul Menzel | 2016-07-31 | 68 | -1000/+1054 |
* | build system: really disable building CrEC when not needed | Patrick Georgi | 2016-07-31 | 2 | -1/+4 |
* | src/arch: Capitalize CPU, RAM and ROM | Elyes HAOUAS | 2016-07-31 | 10 | -18/+18 |
* | src/Kconfig: Capitalize ROM | Elyes HAOUAS | 2016-07-31 | 1 | -1/+1 |
* | src/device: Capitalize CPU, RAM and ROM | Elyes HAOUAS | 2016-07-31 | 3 | -3/+3 |
* | src/cpu: Capitalize CPU | Elyes HAOUAS | 2016-07-31 | 54 | -102/+102 |
* | src/include: Capitalize CPU, RAM and ROM | Elyes HAOUAS | 2016-07-31 | 9 | -19/+19 |
* | src/southbridge: Capitalize CPU, RAM and ROM | Elyes HAOUAS | 2016-07-31 | 18 | -23/+23 |
* | src/northbridge: Capitalize CPU, RAM and ROM | Elyes HAOUAS | 2016-07-31 | 26 | -41/+41 |
* | src/cpu: Capitalize ROM and RAM | Elyes HAOUAS | 2016-07-31 | 12 | -14/+14 |
* | nvidia/tegra124: Adjust memlayout to Chrome OS toolchain | Stefan Reinauer | 2016-07-31 | 1 | -3/+3 |
* | google/gale: Change board ID definition. | Kan Yan | 2016-07-31 | 2 | -3/+6 |
* | Update degree symbol to utf-8 encoding in comments | Martin Roth | 2016-07-31 | 3 | -6/+6 |
* | Remove extra newlines from the end of all coreboot files. | Martin Roth | 2016-07-31 | 109 | -122/+0 |
* | intel/wifi: Include conditionally in the build | Kyösti Mälkki | 2016-07-31 | 7 | -18/+11 |
* | mainboard/bap/ode_e21XX: Add board support | Fabian Kunkel | 2016-07-30 | 12 | -54/+894 |
* | mainboard/bap/ode_e21XX: Add copy of amd/olivehillplus | Fabian Kunkel | 2016-07-30 | 23 | -0/+1823 |
* | chromeos mainboards: remove chromeos.asl | Aaron Durbin | 2016-07-30 | 126 | -675/+514 |
* | google/reef: Use GPE0_DW1_15 as wake signal for touchpad | Furquan Shaikh | 2016-07-30 | 1 | -1/+1 |
* | soc/intel/apollolake: Include gpe.h in chip.h | Furquan Shaikh | 2016-07-30 | 1 | -0/+1 |
* | skylake: fix VSDIO is at 0.8V when SDCard is not inserted | Zhuo-hao.Lee | 2016-07-29 | 1 | -0/+16 |
* | soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume | Abhay Kumar | 2016-07-29 | 3 | -2/+26 |
* | google/gru & kevin: Update DRAM configuration | Lin Huang | 2016-07-28 | 5 | -218/+236 |
* | rockchip/rk3399: sdram: correct controller vref setting | Lin Huang | 2016-07-28 | 1 | -9/+76 |
* | drivers/intel/fsp2_0: Update the copyrights | Lee Leahy | 2016-07-28 | 10 | -8/+25 |
* | google/reef: Write protect GPIO relative to bank offset | Susendra Selvaraj | 2016-07-28 | 1 | -2/+2 |
* | soc/intel/apollolake: Update FSP Header files for version 146_30 | Brandon Breitenstein | 2016-07-28 | 2 | -11/+86 |
* | intel/apollolake: Update gnvs for dptf | Shaunak Saha | 2016-07-28 | 2 | -0/+17 |
* | intel/apollolake: Add soc specific DPTF values | Shaunak Saha | 2016-07-28 | 1 | -0/+44 |
* | intel/common: Add ASL code for DPTF | Shaunak Saha | 2016-07-28 | 5 | -0/+738 |
* | intel/common/opregion.c: only write 16 bytes to 16 byte field | Martin Roth | 2016-07-28 | 1 | -1/+1 |
* | arch/riscv: Refactor bootblock.S | Jonathan Neuschäfer | 2016-07-28 | 3 | -124/+55 |
* | arch/riscv: Only initialize virtual memory if it's available | Jonathan Neuschäfer | 2016-07-28 | 1 | -10/+16 |
* | arch/riscv: Remove spinlock code from atomic.h | Jonathan Neuschäfer | 2016-07-28 | 1 | -29/+0 |