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* drivers/intel/usb4: Add driver for USB4 retimer deviceDuncan Laurie2020-10-195-0/+159
* mb/google/kukui: Support SKU from camera EEPROMHung-Te Lin2020-10-193-3/+103
* drivers/camera: Add config CHROMEOS_CAMERAYu-Ping Wu2020-10-194-0/+74
* mb/google/volteer/elemi: Add memory.c for DDR4Wisley Chen2020-10-192-0/+34
* mb/purism/librem_skl: Clean up FSP-M RCOMP settingsAngel Pons2020-10-191-17/+10
* mb/google/zork/var/vilboz: update dptc stapm timeJohn Su2020-10-191-1/+1
* soc/intel/tigerlake: Reflow long linesSridhar Siricilla2020-10-191-4/+2
* soc/intel/xeon_sp/cpx: Implement platform_fsp_silicon_init_params_cbMarc Jones2020-10-191-1/+3
* cpu/intel,soc/intel: drop Kconfig for hyperthreadingMichael Niewöhner2020-10-178-10/+1
* superio: Add newline to log message about disabled mouse controllerPaul Menzel2020-10-172-2/+2
* mb: AMD CIMx boards: Fix typo in *is defined* in commentsPaul Menzel2020-10-1710-110/+110
* vendorcode/amd: Fix typo in *is defined* in commentsPaul Menzel2020-10-178-62/+62
* AGESA mb: Replace tab with space in macro definition for consistencyPaul Menzel2020-10-1713-13/+13
* vc/amd/Kconfig: Add missing dot in AMD domain www.amd.comPaul Menzel2020-10-171-1/+1
* superio/nuvoton: Only set bit 7 of global CR 0x2a for COM APaul Menzel2020-10-171-1/+1
* intel/txt: Add `txt_get_chipset_dpr` functionAngel Pons2020-10-174-10/+60
* security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]Angel Pons2020-10-171-17/+86
* sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACMAngel Pons2020-10-171-0/+12
* trogdor/sc7180: Clarify USE_QC_BLOBS requirementsJulius Werner2020-10-172-5/+13
* include/cpu/x86: introduce new helper for (un)setting MSRsMichael Niewöhner2020-10-166-22/+48
* soc/intel/skylake: Rename PcieRpAspm devicetree configBenjamin Doron2020-10-163-6/+6
* acpi/acpigen_dsm: fix I2C HID DSM to report correct function supportJosie Nordrum2020-10-161-12/+11
* mb/google/zork: disable eMMC per FW_CONFIG for berknipKevin Chiu2020-10-162-0/+17
* mb/intel/adlrvp: Enable Hybrid storage modeSubrata Banik2020-10-161-0/+2
* mb/intel/adlrvp: Enable PCIE RP11 for optaneSubrata Banik2020-10-161-1/+4
* mb/intel/adlrvp: Fix SSD detection issue on ADL RVPSubrata Banik2020-10-161-2/+2
* mb/intel/adlrvp: Program GPIO for M.2 PCH SSDSubrata Banik2020-10-161-0/+4
* lib and libpayload: Add popcnt functionsAngel Pons2020-10-151-0/+3
* soc/intel/xeon_sp: Add get_system_memory_map()Marc Jones2020-10-153-5/+15
* ec/google/chromeec: Update ec_commands.hYidi Lin2020-10-151-2/+226
* Update bit field helpers to support more bit field operateHuayang Duan2020-10-151-2/+25
* sec/intel/txt/getsec_enteraccs.S: Save and restore MTRR_DEF_TYPEArthur Heymans2020-10-151-6/+2
* nb/intel/haswell: Account for DPR region in memory mapAngel Pons2020-10-153-11/+62
* security/intel/txt: Use `smm_region()` to get TSEG baseAngel Pons2020-10-152-5/+16
* soc/intel/skylake: Configure L1 substates for PCH root portsBenjamin Doron2020-10-152-0/+10
* soc/intel/skylake/cpu.c: Fix comment coding styleAngel Pons2020-10-141-4/+4
* mb/google/volteer: Disable HybridStorageMode for volteer baseboardShaunak Saha2020-10-143-1/+5
* lib and libpayload: add 64-bit versions of clz, __ffs and log2Tim Wawrzynczak2020-10-141-0/+4
* mb/intel/adlrvp: Add ADL-P mainboard ASL codeSubrata Banik2020-10-141-0/+32
* mb/intel/adlrvp: Add ADL-P ramstage mainboard codeSubrata Banik2020-10-149-4/+594
* soc/intel/jasperlake: Enable CAR NEM enhanced modeAamir Bohra2020-10-141-1/+2
* nb/intel/x4x: Place raminit definitions in raminit.hAngel Pons2020-10-148-245/+259
* nb/intel/x4x: Move register headers into a subfolderAngel Pons2020-10-142-4/+4
* mb/purism/librem_skl: Drop DQ and DQS byte mapsAngel Pons2020-10-141-26/+0
* nb/intel/x4x: Clean up DMIBAR/EPBAR definitionsAngel Pons2020-10-142-44/+92
* soc/intel/broadwell/xhci.c: Align with Lynx PointAngel Pons2020-10-141-8/+2
* soc/intel/broadwell/smi.c: Drop unused functionsAngel Pons2020-10-141-32/+0
* soc/intel/broadwell/pcie.c: Add some null checksAngel Pons2020-10-141-1/+4
* haswell/lynxpoint: Align cosmetics with BroadwellAngel Pons2020-10-1413-150/+151
* soc/intel/broadwell: Align cosmetics with Haswell/Lynx PointAngel Pons2020-10-1410-76/+60
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