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* mb/prodrive/atlas: Add data.vbt for 4 DPs supportLean Sheng Tan2022-06-052-2/+3
| | | | | | | | Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/octopus: Demote NHLT log messages from error to infoMatt DeVillier2022-06-051-5/+5
| | | | | | | | | Change-Id: Ib2d0c6a23b66e6e61cc8ea09a443e19a4b37c66d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/prodrive/atlas: Update pcie config for i225Lean Sheng Tan2022-06-051-3/+4
| | | | | | | | | | Enable clk 1, LTR & AER for PCIe-to-i225 bridge. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/prodrive/atlas: Fix FSP debug boot hangLean Sheng Tan2022-06-051-0/+1
| | | | | | | | | | | | | | | When device tcss_xhci is disabled, boot hang occurs at FSP-S TcssInit(): "IomReadyCheck Failed!" Enabling this device fixes the issue. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ie001bd56b403d511c397737fbc214ed64956910d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64901 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/prodrive/atlas: Add display configs for 4 DisplayPortsLean Sheng Tan2022-06-051-0/+8
| | | | | | | | Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Iea5312055305bc3354755607a7bfafa7980c6d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* soc/intel/elkhartlake: Remove board related vboot kconfigs from socLean Sheng Tan2022-06-051-2/+0
| | | | | | | | | | | | | | Since the non-volatile storage as it handles VBNV storage in either flash or CMOS, is chosen based on board design, removing VBOOT_VBNV_CMOS & VBOOT_VBNV_CMOS_BACKUP_TO_FLASH from EHL soc kconfig. Will add the option to EHL CRB mainboard kconfig later. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I97fb7017bff7751d64571d1a8ee7c8b9e2771731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64473 Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/kinox: Update gpio configurationDtrain Hsu2022-06-051-4/+4
| | | | | | | | | | | | | | | | | Follow GPIO_Table_0527.xlsx to update gpio configuration. - Set GPP_A15 to NC. - Set GPP_A20 to TCP_DP1_HPD (native function1). BUG=b:225384873 TEST=Build and boot to Chrome OS. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I1c7a211c3bef1f1fe4f94345186c33363a90e11f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/cmn/cse: Fix return type for `devfn`Subrata Banik2022-06-041-1/+1
| | | | | | | | | | | | | | | | This patch fixes the return type for `devfn` variable inside heci_set_to_d0i3(). `PCI_DEVFN` macro returns `unsigned int` instead of `pci_devfn_t`. TEST=Able to build and boot to ChromeOS without any failure. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib3a575aa7d71cbe6932e823917b57c5558387433 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* soc/intel: Rename heci_init to cse_initSubrata Banik2022-06-049-11/+15
| | | | | | | | | | | | | | | | | This patch renames heci_init() to cse_init() as HECI initialization should have a bigger scope than just initializing the CSE (a.k.a HECI1 alone). BUG=none TEST=Able to build and boot google/taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* cpu/x86/smm_module_loader: Use struct region in cpu mapArthur Heymans2022-06-031-28/+17
| | | | | | | | | | | | We use a region later on so we might as well use a region from the start. This simplifies the computations too. Change-Id: Iffa36ccb89c36401d3856b24364216e83ca35f91 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64609 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* cpu/x86/smm: Use struct region to check overlapping sectionsArthur Heymans2022-06-031-149/+119
| | | | | | | | | | | | | | | | | | | This allows for some runtime checks on all SMM elements and removes the need for manual checks. We can drop completely separate codepaths on SMM_TSEG & SMM_ASEG as the only difference is where permanent handler gets placed. TESTED on prodrive/hermes and qemu with SSM_ASEG with 4 cores & SMM_TSEG with 128 cores. This code figured out quite some problems with overlapping regions so I think this is the right approach. Change-Id: Ib7e2e3ae16c223ecfd8d5bce6ff6c17c53496925 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63602 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* ec/google/chromeec/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer2022-06-031-1/+1
| | | | | | | | | | Replace `LGreater(a, b)` with `a > b`. Change-Id: Ie6238ead464d79b3576846f3b5b92b658972eec8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driverSubrata Banik2022-06-033-8/+9
| | | | | | | | | | | | | | | | | | | | | This patch removes the MTL CNVi DIDs macros from IA common code and is added into the generic wifi driver. As per Intel Connectivity Platform BIOS Guide, Connectivity Controller IP for MTL-P is `Magnetar` and supported CRF is `Typhoon Peak 2`. Previously Garfield Peak DIDs for Alder Lake SoC also added similarly to generic wifi drivers. BUG=b:224325352 TEST=Able to build and boot on MTL emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib98762749c71f63df3e8d03be910539469359c68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
* ec/acpi: Rework to reduce code duplicationAbel Briggs2022-06-032-51/+60
| | | | | | | | | | | | | | | | | | | - Move EC send/receive polling code to their own functions - Add named constants for poll timeouts and delay interval - Use human-readable timeout values - Add `send`/`recv` functions which support custom timeouts - Remove extra 10us delays between polling and performing a given transaction - Use constants from `ec.h` for standard EC command opcodes Tested on a Lenovo Edge E530, which takes similar code paths to the Lenovo Twist S230u. Change-Id: Ifda5c030ff81f1046be58aa1fcafdcf71a27cd41 Signed-off-by: Abel Briggs <abelbriggs1@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/google/brya/var/mithrax: Update DPTF parameters for MithraxJohn Su2022-06-031-5/+5
| | | | | | | | | | | | | | | | | Follow thermal table from thermal team. Chang list: 1. Update TEMP_PCT of Active Policy for TSR1. BUG=b:230829301 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/mediatek: Rename mtk_wdt_preinit() to mtk_wdt_set_req()Rex-BC Chen2022-06-036-5/+7
| | | | | | | | | | | | | | | | | | To simplify the calling sequence for mtk_wdt_preinit() and we always adjust request setting in mtk_wdt_preinit(), we rename mtk_wdt_preinit() to mtk_wdt_set_req() and call it in mtk_wdt_init(). From this modification, we can also enable thermal hardware reset feature (CB:64676, CB:64675) in MT8192 and MT8195. BUG=none TEST=build pass Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* intelblocks/gpio.c: Handle NULL return values from child functionsMaulik V Vaghela2022-06-031-1/+13
| | | | | | | | | | | | | | | | | | | | gpio_configure_pad function gets called for most of the GPIO configuration for all the boards. This function is not handling NULL pointers properly which can cause exception in CPU. This patch fixes the handling and function is able to return early in case the NULL pointer is passed or any subsequent child function calls return NULL. BUG=None BRANCH=None TEST=Compilation works fine for all Alder Lake boards. Change-Id: I97fad72cdd92f70c7c5e6fdd23fbecf535a6e388 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/variants/nereid: Add DPTF passive and critical policies for ↵Vidya Gopalakrishnan2022-06-031-0/+52
| | | | | | | | | | | | | | | | | | | Nereid BUG=b:233030505 BRANCH=None TEST=Build FW and test on Nereid board. Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: I195f4b507ee57948751f0119735d8350dfce984b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
* ec/google/chromeec/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer2022-06-031-1/+1
| | | | | | | | | | Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Iea86e77df6c76756ed336f57a906ac0757aef1cf Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec/acpi: Replace Divide(a,b,,c) with ASL 2.0 syntaxFelix Singer2022-06-032-6/+6
| | | | | | | | | | Replace `Divide (a, b, , c)` with `c = a / b`. Change-Id: I26117087c09109cfc480cbe01d3761a02a12c61b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-034-11/+11
| | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I4d79080ecfe457766983b20a0217ccadcd188fcf Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer2022-06-031-1/+1
| | | | | | | | | | Replace `LLess(a, b)` with `a < b`. Change-Id: I65225a890f9085574a2295e6ccd2cdc3e84f71e0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* arch/x86/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer2022-06-032-3/+3
| | | | | | | | | | Replace `LGreater(a, b)` with `a > b`. Change-Id: I0cabf4f69191fe345fd72619847db384db2e0e87 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-031-1/+1
| | | | | | | | | | Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I72875f68e143f9384c91588cd453d2987fda526d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* cpu/x86/smm_module_loader: Update loggingArthur Heymans2022-06-031-1/+1
| | | | | | | | | | | | Some logging is superfluous and logging that code is being copied is 'SPEW' level. Change-Id: I84d49a394cc53d78f1e1d3936502ac16810daf9f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSxTyler Wang2022-06-031-0/+15
| | | | | | | | | | | | | | | | | | | | This patch configures external V1p05/Vnn/VnnSx rails for Craask to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:233717182 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* soc/intel/elkhartlake: Select SOC_INTEL_RAPL_DISABLE_VIA_MCHBARUwe Poeche2022-06-031-0/+1
| | | | | | | | | | | | | | | | Since of moving RAPL disabling to common code a config switch is available to select that RAPL disabling has to be done via MCHBAR. This patch selects the switch for EHL. Test: Boot mc_ehl1 and ensure that relevant bits in MCHBAR are the same as before the patch. Change-Id: I1d0b7f650aa3ccf89c5c35d9b60a83a1ce48c74f Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/google/nissa/var/nivviks: Enable ISH when UFS is presentReka Norman2022-06-031-0/+3
| | | | | | | | | | | | | | | | | | | | | In order to enable the UFS controller (PCI device 12.7), the PCI specification says that the device at function 0 in the same slot must also be enabled, which is the ISH. Therefore, enable ISH when UFS is present. For more context on why this is necessary, see CB:62662 which enabled UFS and ISH for adlrvp_n. BUG=b:234136500 TEST=Build test. Will test that UFS works once we have hardware. Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: Ib60d44322cfbd8f82c33ecac7598881dfb1d0c3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Daniil Lunev <dlunev@chromium.org>
* amdblocks/smm.h: Add header guardsArthur Heymans2022-06-031-0/+5
| | | | | | | | | | Change-Id: I5d01c36fa4695ee42d18701a90d1b96bceb5045f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* intel/common/block: move RAPL disabling to common codeUwe Poeche2022-06-034-21/+32
| | | | | | | | | | | | | | | | | | This patch brings the feature of disabling RAPL to common code. It replaces the current solution for APL and EHL. For special case if RAPL disabling is only working via changes in MCHBAR a new config switch was introduced. Test: Boot mc_apl4/5 with this patch and ensure that the relevant bits in MSR 0x610 are the same as before the patch. Change-Id: I2098ddcd2f19e3ebd87ef00c544e1427674f5e84 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/purism/librem_mini: Hide Linux GPIO LED from WindowsMatt DeVillier2022-06-021-0/+1
| | | | | | | | | | | | | | | | | Hide the Linux gpio-led ACPI device from Windows by setting the device status (_STA) to 0xB (enabled, hidden) so Windows doesn't show an unknown device/missing drivers in Device Manger. Linux doesn't care about the _STA value. Test: build/boot Windows (10/11) and Linux (PureOS 10) on a Librem Mini v2, verify LED works under Linux, is ignored under Windows Change-Id: If3ee0db685a2f7dab505602afa98c3c2d5adf5d3 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/google/brya: Add new skolas baseboardNick Vaccaro2022-06-0220-1/+2176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the skolas baseboard, which is basically the brya baseboard, but using an Intel Raptor Lake-P SoC instead of an Alder Lake SoC. This commit also adds the skolas baseboard variant skolas4es. Since this baseboard is identical to the brya baseboard with the exception of the SoC used, the new baseboard and the new baseboard's first variant will be a copy of the current brya baseboard and brya0 variant. For now, the skolas baseboard and skolas4es variant will continue to use ADL-P. This allows for two benefits: 1. software to be proven out on existing hardware prior to RPL SoC support landing, and 2. allows us not to have to wait for RPL SoC changes prior to getting the mainboard changes in place Once the RPL SoC code has merged, I will update the skolas baseboard and skolas4es variant to use RPL instead of ADL. BUG=b:229134437 TEST=util/abuild/abuild -p none -t google/brya -x -a -c max Change-Id: Iec100306dca2320eaf2432797f3acc31db2543d3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* cpu/x86/mp_init.c: Prolong delay on synchronous APIArthur Heymans2022-06-022-3/+3
| | | | | | | | | | | When each AP needs to do a lot of printing 1 sec is not enough. Change-Id: I00f0a49bf60f3915547924c34a62dd0044b0c918 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64828 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
* mb/google/brya/variants/osiris: Remove KB_MT from overridetreeDavid Wu2022-06-021-4/+0
| | | | | | | | | | | | | | All Osiris SKUs use the new RGB gaming keyboard, so don't need the fw_config to decide keyboard matrix. BUG=b:220800586 TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19211c345de0b315d65ec64efc70826e81315810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
* soc/intel/alderlake: add power limits for Alder Lake-N SKUsVidya Gopalakrishnan2022-06-022-0/+26
| | | | | | | | | | | | | | | | This patch adds support for the ADL-N SKUs based on the PCH ID. Document reference: 645548 (ADL-N EDS Volume 1). BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Change-Id: I24c18a27a4a2c68c78bc3dc728c45ba04f57205d Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64472 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/intel/adlrvp: Enable DPTF for ADL-N RVPVidya Gopalakrishnan2022-06-021-0/+101
| | | | | | | | | | | | | | | BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Verified fan control successfully when participant reaches temp threshold as per Active Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Icafacfca6a026ec3b42906790831f11fd2f1b085 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/intel/adlrvp: Set power limits dynamically for ADL-N SKUsVidya Gopalakrishnan2022-06-021-0/+4
| | | | | | | | | | | | | | | | This patch adds support for the ADL-N SKUs based on the PCH ID. Document reference: 645548 (ADL-N EDS Volume 1). BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Ie49398b8a7de8d8cff3536eae6a5e893980f9c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik2022-06-0212-0/+101
| | | | | | | | | | | | | | | | This patch implements a SoC overrides to set CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* cpu/intel/model_fxx: Select SSE2Arthur Heymans2022-06-023-0/+3
| | | | | | | | | | | | | Starting from Intel Pentium 4, cpus featured SSE2. This will be used in the follow-up patches to determine whether to use mfence as this instruction was introduced with the SSE2 feature set. Change-Id: I8ce37d855cf84a9fb9fe9e18d77b0c19be261407 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* cpu/x86/smm_module_loader: Drop superfluous checksArthur Heymans2022-06-021-47/+5
| | | | | | | | | | | Checking if the stack encroaches on the entry points is done in other parts of the code. Change-Id: I275d5dda9c69cc89608450ae27dd5dbd581e3595 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mb/google/nissa/var/craask: Disable PCIe WLAN pinsTyler Wang2022-06-021-0/+4
| | | | | | | | | | | | | | Craask uses CNVi WLAN, so disable the PCIe-related GPIOs. BUG=b:229040345 Test=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I7bcf041503dcee448758dac46b1c9711d0b02ba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* nb/intel/i440bx: Use PARALLEL_MPArthur Heymans2022-06-022-6/+15
| | | | | | | | | | | | The ramstage size is decreased by roughly 5K, but the compressed size increased by ~1K. Change-Id: Ic8d2582b353069eecea8561cfe01b2dd8221779b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59693 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/mp.h: Implement a pre-SSE2 mfenceArthur Heymans2022-06-021-1/+5
| | | | | | | | | | | | Taken from the Linux Kernel. Tested: Qemu using '-cpu pentium3' now boots. Change-Id: I376f86f4d7992344dd68374ba67ad3580070f4d8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mb/lenovo/w541/Kconfig: sort alphabeticallyPeter Lemenkov2022-06-011-1/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I9cefa29738b42dd08cb00489ad6e8644e3fc405e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/t440p/Kconfig: remove duplicates and sort alphabeticallyPeter Lemenkov2022-06-011-3/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I47fded50377ab624e4bceb320a5e069a7f36c2fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/t440p/hda_verb: WhitespacePeter Lemenkov2022-06-011-1/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I92c167bf95e605e098324b9e80cfaab8f589dcab Reviewed-on: https://review.coreboot.org/c/coreboot/+/63995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/w541/hda_verb: WhitespacePeter Lemenkov2022-06-011-1/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I284a5e39ca4b0032ed0c8e3a92c095db319d1691 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/w541/dsdt.asl: Remove redundant commentFelix Singer2022-06-011-1/+0
| | | | | | | | | Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: Ide938a40ed1f6869ee248ed46f6bf29f95649490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/t440p/cmos: Remove unused optionsPeter Lemenkov2022-06-011-4/+0
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I9bf95ed74468e283bab79a5f25aee758d37d926a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verificationJulius Werner2022-06-012-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel Firmware Interface Table (FIT) is a bit of an annoying outlier among CBFS files because it gets manipulated by a separate utility (ifittool) after cbfstool has already added it to the image. This will break file hashes created for CBFS verification. This is not actually a problem when booting, since coreboot never actually loads the FIT from CBFS -- instead, it's only in the image for use by platform-specific mechanisms that run before coreboot's bootblock. But having an invalid file hash in the CBFS image is confusing when you want to verify that the image is correctly built for verification. This patch adds a new CBFS file type "intel_fit" which is only used for the intel_fit (and intel_fit_ts, if applicable) file containing the FIT. cbfstool will avoid generating and verifying file hashes for this type, like it already does for the "bootblock" and "cbfs header" types. (Note that this means that any attempt to use the CBFS API to actually access this file from coreboot will result in a verification error when CBFS verification is enabled.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1c1bb6dab0c9ccc6e78529758a42ad3194cd130c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 13:11:35 +0000