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* mb/lenovo/*/dsdt: Remove HAVE_LCD_SCREENPeter Lemenkov2018-10-152-2/+0
* mb/asus/p5q_pro: Add mainboardArthur Heymans2018-10-154-2/+143
* drivers/net/atl1e: Add driverArthur Heymans2018-10-154-0/+207
* mb/asus/p5qc: Add mainboardArthur Heymans2018-10-1518-0/+771
* vc/google/chromeos/ec: remove EC hibernate in cr50 update pathAaron Durbin2018-10-153-16/+1
* nb/intel/x4x: Fix P45 CAPID max frequencyArthur Heymans2018-10-151-0/+1
* sb/intel/i82801jx: Use macros for LPC_ENArthur Heymans2018-10-152-1/+14
* nb/intel/x4x: Program read training results to all ranksArthur Heymans2018-10-151-3/+9
* soc/amd/stoneyridge: Define PM USB Enable registerMarshall Dawson2018-10-142-2/+4
* soc/amd/stoneyridge: Remove hudson EHCI debug controllersMarshall Dawson2018-10-141-6/+2
* soc/amd/stoneyridge: Remove errant parenthesis in southbridge.hMarshall Dawson2018-10-141-1/+1
* soc/amd/stoneyridge: Rearrange southbridge.h moreMarshall Dawson2018-10-141-7/+7
* drivers/intel/fsp2_0: Hook up IntelFSP repoPatrick Georgi2018-10-1222-14250/+65
* libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2Julius Werner2018-10-121-0/+4
* amd/stoneyridge: Fix PmControl register size in SMI handlerMarshall Dawson2018-10-121-5/+5
* amd/stoneyridge: Rename CGPLL_CONFIG definitionsMarshall Dawson2018-10-122-35/+34
* amd/stoneyridge: Rename GppClkCntrl fieldsMarshall Dawson2018-10-122-12/+12
* amd/stoneyridge: Rearrange southbridge.hMarshall Dawson2018-10-121-122/+130
* amd/stoneyridge: Remove dead GPIO definitionsMarshall Dawson2018-10-121-6/+0
* amd/stoneyridge: Clarify XHCI_PM register definitionsMarshall Dawson2018-10-121-17/+16
* amd/stoneyridge: Fix SPI_CMD_TRIGGER coding styleMarshall Dawson2018-10-121-2/+2
* amd/stoneyridge: Convert hex definitions to lower caseMarshall Dawson2018-10-124-24/+24
* amd/stoneyridge: Remove hudson register definitionsMarshall Dawson2018-10-121-5/+0
* mb/google/poppy/var/nocturne: Provide override for ec eventinfoFurquan Shaikh2018-10-113-1/+40
* mb/google/poppy: Allow variants to provide event info at runtimeFurquan Shaikh2018-10-114-9/+33
* ec/google/chromeec: Add support for querying ec board id in smm stageFurquan Shaikh2018-10-111-0/+1
* ec/google/chromeec: Get rid of __SMM__ guard for chromeec functionsFurquan Shaikh2018-10-111-6/+0
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-1156-265/+130
* src: Replace MSR addresses with macrosElyes HAOUAS2018-10-114-11/+11
* amd/stoneyridge: Indicate STAPM units in their nameRichard Spiegel2018-10-114-10/+11
* mainboard/google/kahlee: Set PSPP setting to BalanceLowAkshu Agrawal2018-10-111-1/+1
* mb/google/kahlee: Set stapm parameters with time value fixedAkshu Agrawal2018-10-112-10/+6
* selfboot: remove bounce buffersRonald G. Minnich2018-10-1113-675/+124
* tegra124_lp0: make sure to build with compiler.h includedPatrick Georgi2018-10-111-0/+1
* commonlib/storage: Make pci sdhci code compile in romstageBora Guvendik2018-10-111-8/+14
* riscv: add physical memory protection (PMP) supportXiang Wang2018-10-113-0/+355
* soc/intel/common/block/gpio: check for NULL using if statementBora Guvendik2018-10-111-1/+2
* mb/google/octopus: I2C clock tuning for meepWisley Chen2018-10-111-0/+41
* mb/cavium/cn8100_sff_evb: Only expose two UARTsPatrick Rudolph2018-10-111-2/+2
* soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabledFurquan Shaikh2018-10-101-0/+25
* mb/google/octopus: Drop I2C bus 0 clock frequency for Phaserpeichao.wang2018-10-101-2/+2
* lib: increase part number size in memory_info/dimm_infoAaron Durbin2018-10-101-1/+1
* soc/cavium: dynamic UART initialization for cavium cn8100Jens Drenhaus2018-10-103-12/+28
* mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPDChris Zhou2018-10-102-1/+33
* mb/google/kahlee/variants/*/devicetree.cb: Reset I2C slavesRichard Spiegel2018-10-104-0/+12
* soc/amd/stoneyridge/gpio.c: Create I2C slave reset codeRichard Spiegel2018-10-104-0/+149
* mb/google/kahlee: Add delan variantMartin Roth2018-10-1012-0/+341
* mb/google/fizz: Prepare sharing directory for variantsDavid Wu2018-10-102-7/+9
* mediatek/mt8183: Init PLLs for DRAMTristan Shieh2018-10-102-9/+15
* soc/intel/cannonlake: Add PCIE ASL entrySubrata Banik2018-10-092-0/+385
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