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* soc/fsp_broadwell_de: Add support for GPIO handlingWerner Zeh2017-10-197-0/+275
* cpu/x86: add AMD registers to SMM save stateJohn E. Kabat Jr2017-10-191-1/+6
* sb/intel/bd82x6x: Add new USB currentsVagiz Trakhanov2017-10-191-1/+3
* nb/sandybridge: Add a kconfig option to ignore XMP max DIMMsVagiz Trakhanov2017-10-192-1/+13
* src/vendorcode/amd: Use AR variable in MakefilesMartin Roth2017-10-196-6/+6
* AGESA f14: Fix DDI maps in OemCustomize.cKyösti Mälkki2017-10-197-28/+14
* AGESA: Split long lines in OemCustomize.cKyösti Mälkki2017-10-1917-91/+440
* AGESA f14: Drop PlatformGnbPcieComplex.hKyösti Mälkki2017-10-1922-828/+101
* pcengines/apu2: Add timestamps to romstageMichał Żygowski2017-10-191-0/+11
* Enable time stamp collection by default on x86Paul Menzel2017-10-191-0/+1
* google/chromeec: Do not set wake mask before logging EC eventsFurquan Shaikh2017-10-192-4/+14
* mb/google/poppy: Log EC events during S0ix resumeFurquan Shaikh2017-10-193-0/+12
* ec/google/chromeec: Export google_chromeec_log_events in ec.hFurquan Shaikh2017-10-192-1/+4
* soc/intel/skylake: Probe XHCI for wake source for Internal PMEFurquan Shaikh2017-10-191-0/+10
* soc/intel/skylake: Prevent false logs in pch_xhci_port_wake_checkFurquan Shaikh2017-10-191-0/+5
* soc/intel/skylake: Define mask for SMI handlers that can be run in SCI modeFurquan Shaikh2017-10-191-0/+18
* soc/intel/skylake: Support logging wake source in SMMFurquan Shaikh2017-10-192-0/+9
* soc/intel/skylake: Move power_state functions to pmutil.cFurquan Shaikh2017-10-193-106/+68
* soc/intel/skylake: Use PCH_DEV_* instead of PCH_DEVFN_*Furquan Shaikh2017-10-191-25/+24
* soc/intel/skylake: Use newly added pmc_read_pm1_controlFurquan Shaikh2017-10-191-3/+2
* soc/intel/apollolake: Use newly added pmc_read_pm1_controlFurquan Shaikh2017-10-191-1/+1
* soc/intel/common/block/pmc: Add helper routines to read/write PM1_CNTFurquan Shaikh2017-10-192-9/+24
* soc/intel/common/block/pmc: Add new function pmc_fill_pm_reg_infoFurquan Shaikh2017-10-192-2/+15
* elog: Support logging S0ix sleep/wake info in elogFurquan Shaikh2017-10-192-0/+41
* mainboard/intel/cannonlake_rvp: Enable hardware P state controlVaibhav Shankar2017-10-182-0/+6
* arch/x86: restore forwarding table on resume for EARLY_EBDA_INITAaron Durbin2017-10-182-1/+45
* soc/intel/cannonlake: Set platform Debug Probe TypeLijian Zhao2017-10-182-0/+11
* intel/cannonlake_rvp: Enable Audio DSPLijian Zhao2017-10-182-0/+6
* intel/cannonlake_rvp: Declare PCIE clock usageLijian Zhao2017-10-182-0/+60
* soc/intel/cannonlake: Update PCIE CLKREQ programingLijian Zhao2017-10-184-4/+36
* soc/intel/cannonlake: Add finalize functionLijian Zhao2017-10-184-0/+263
* google/snappy: Override USB2 strength by SKUIDKevin Chiu2017-10-181-0/+37
* mb/google/fizz: skip reading SPD data when DUT resumes from S3Gaggery Tsai2017-10-181-0/+5
* soc/intel/cannonlake: Calculate soc reserved memory sizeSubrata Banik2017-10-181-0/+15
* soc/intel/cannonlake: Use EBDA area to store cbmem_top addressSubrata Banik2017-10-185-49/+76
* soc/intel/cannonlake: Refactor memory layout calculationSubrata Banik2017-10-181-48/+119
* soc/intel/cannonlake: Create acpi_get_sleep_type() to get previous sleep stateSubrata Banik2017-10-181-2/+8
* google/chromeec: Drain all MKBP events while clearing host eventsFurquan Shaikh2017-10-181-0/+5
* google/chromeec: Add new helper function to read MKBP eventsFurquan Shaikh2017-10-182-0/+21
* intel/cannonlake_rvp: enable HS400Bora Guvendik2017-10-172-0/+2
* soc/amd/stoneyridge: clean up chip.hMartin Roth2017-10-171-6/+0
* soc/intel/common/block/pmc: Move pmc_disable_all_gpe to romstageFurquan Shaikh2017-10-172-3/+15
* amd/agesa: Remove redundant UDELAY_LAPIC selectionPaul Menzel2017-10-175-5/+0
* sandybridge/acpi: remove unnessary check of PCI IDsVagiz Trakhanov2017-10-162-7/+2
* nb/intel: Add Ivy Bridge Server (Xeon-E3v2) PCI IDsVagiz Trakhanov2017-10-163-1/+9
* arch/x86: initialize EBDA in S3 and S0/S5 pathAaron Durbin2017-10-161-5/+0
* soc/intel/common: sanity check ebda signatureAaron Durbin2017-10-163-2/+15
* drivers/elog: Fix debug build errorsJohn E. Kabat Jr2017-10-162-2/+3
* intel/cannonlake_rvp: Modify memory parameters to support LP4 boardLijian Zhao2017-10-162-34/+10
* cpu/amd: Fix spelling of *implementation*Paul Menzel2017-10-162-2/+2
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