summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* soc/intel/{adl,common}: Support alderlake host device id 0x4619Kane Chen2022-01-183-0/+3
| | | | | | | | | | | | | | Host device id 0x4619 is missed in few coreboot tables so that coreboot can't recognize and config it properly. Document Number: 690222 BUG:b:214665785, b:214680767 Change-Id: I95908bdc0a736bafedb328dda2a00b5473de3d88 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* sb/intel/common/firmware: Reword me_cleaner warningAngel Pons2022-01-171-1/+1
| | | | | | | | | | | | | | | | | | | That vendor firmware still works after applying `me_cleaner` doesn't mean that coreboot will also work with the same broken ME firmware. Instead, one should first test coreboot with the original, unmodified ME firmware to make sure coreboot works properly, and only then consider using `me_cleaner` with coreboot. Otherwise, one would end up with a non-booting or otherwise misbehaving system when trying to use coreboot and `me_cleaner` without having tested coreboot with the original ME firmware beforehand, which is hard to diagnose as the problem may only happen when the ME isn't running normally. Change-Id: I1626d747a99969faf7db37c10cf7d87e3977744a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/google/auron: Remove addition of EC firmware to buildTim Wawrzynczak2022-01-171-5/+0
| | | | | | | | | | | | | | | In https://crrev.com/c/3069716, the samus EC firmware was removed from the `main` branch, therefore in order to update the `chromeec` 3rdparty submodule, the automatic build and inclusion of samus EC firmware into coreboot's `master` branch has to be dropped as well. Change-Id: I6fcdd3b7925b6ec33ba48892ed750c29bb60634c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* cr50: Increase cr50 i2c probe timeoutRob Barnes2022-01-171-2/+2
| | | | | | | | | | | | | | | | | | | | Turns out 150ms isn't enough in the worst reset conditions. On guybrush the TPM is reset in S0i3 and the CR50 is allowed to hibernate. The CR50 is woken up and initialized early during S0i3 resume. Occasionally the CR50 isn't ready before the probe times out. BUG=b:213828947 BRANCH=None TEST=suspend_stress_test -c 1000 Change-Id: Ifda438080cf1ad2796c7061223a6a97b8e6e9987 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* drivers/intel/fsp2_0: Add FSP 2.3 supportAnil Kumar2022-01-175-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | FSP 2.3 specification introduces following changes: 1. FSP_INFO_HEADER changes Updated SpecVersion from 0x22 to 0x23 Updated HeaderRevision from 5 to 6 Added ExtendedImageRevision FSP_INFO_HEADER length changed to 0x50 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 Following changes are implemented in the patch to support FSP 2.3: - Add Kconfig option - Update FSP build binary version info based on ExtendedImageRevision field in header - New NV HOB related changes will be pushed as part of another patch Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/variants/*: Add cpu pcie rp flagsTracy Wu2022-01-178-0/+10
| | | | | | | | | | | | | | | | | | Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs), we need to set cpu pcie rp flags in devicetree now. This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in all intel projects or system will be blocked at PKGC2R with root port LTR not enable. BUG=b:214009181 TEST=Build and DUT (Kano) can enter deeper PKGC state normally. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/taeko4es: Enable Bayhub LV2 driverKevin Chang2022-01-171-0/+1
| | | | | | | | | | | | | | Some SKUs of google/taeko4es have a Bayhub LV2 card reader chip, therefore enable the corresponding driver for the mainboard. BUG=b:204343849 TEST=Build FW and checking SD card reader register is correct. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I3d2ea3db9df38e7b0cac4c32e1fca579ff43e5bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/var/bugzzy: Set core display clock to 172.8 MHzSeunghwan Kim2022-01-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | When using the default initial core display clock frequency (648MHz), Jasper Lake board might have a rare stability issue where the startup of Chrome OS in secure mode may hang during re-initializing display in kernel graphic driver. Bugzzy didn't show this problem so far, but Intel recommends slowing the initial core display clock frequency down to 172.8 MHz to prevent this potential problem. Depend on CL: https://review.coreboot.org/c/coreboot/+/60009 The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0 (172.8 MHz) for bugzzy. BUG=None BRANCH=dedede TEST=Build firmware and check the DUTs can boot up in secure mode well. Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* pci_ids.h: Make Denverton IDs consistent with other Intel SoCsJeff Daly2022-01-1710-44/+44
| | | | | | | | | | | Align Denverton PCI ID define names with other Intel SoCs. Also, update the names in SoC code accordingly. Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/cnl: Use Kconfig to disable HECI1Subrata Banik2022-01-177-9/+9
| | | | | | | | | | | | | This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake and ensures disable_heci1() is guarded against this config. Also, makes dt CSE PCI device `on` by default. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Revert "mb/google/dedede/var/beadrix: Remove SD controller"Teddy Shih2022-01-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bcd7873ea80be0ee576a10e6a11b7dcf8294ffb5. Reason for revert: It makes beadrix can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants. ================ error log ================ ... Starting depthcharge on Beadrix... src/vboot/util/flag.c:50 flag_install(): Gpio already set up for flag 5. =========================================== BUG=b:204882915 BRANCH=None TEST=Build and boot into OS. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Id5e76fc78a56d30caf9f805a8a430f176a653bbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/60849 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/beadrix: Add memory part and generate DRAM IDTeddy Shih2022-01-173-6/+17
| | | | | | | | | | | | | | | | This change adds memory part used by variant beadrix to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:204882915, b:210123929 BRANCH=None TEST=Run part_id_gen to generate SPD id Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibff150bb4e742f32641da661cfca6594d18c52e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60242 Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/agah: update gpio overrideTony Huang2022-01-172-0/+216
| | | | | | | | | | | | | Configure GPIOs according to schematics BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: Icfd1e09761e51aca9c23f3ab340adac7a66a3ada Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* console: Add Kconfig to dump pre-bootblock cbmem contentsRaul E Rangel2022-01-172-0/+12
| | | | | | | | | | | | | | | | | | | | | | | Pre-bootblock stages (i.e., VBOOT_STARTS_BEFORE_BOOTBLOCK) might not have the ability to log to the UART, so their console messages are inaccessible until the boot processes gets into the payload or OS. This makes it difficult to debug verstage. This feature will dump the pre-bootblock CBMEM console immediately after the bootblock console is initialized. I chose to do this in console_init instead of bootblock_soc_init because I wanted to have the pre-bootblock contents dumped before the coreboot bootblock starting message is printed. BUG=b:213828947 TEST=Boot guybrush with PSP verstage and verify verstage logs are dumped to the UART. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I363c93ef3ee6c5c303a6a68f88a622e2aa62594c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61012 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console/cbmem: Add cbmem_dump_consoleRaul E Rangel2022-01-172-1/+24
| | | | | | | | | | | | | | | | This function is similar to cbmem_dump_console_to_uart except it uses the normally configured consoles. A console_paused flag was added to prevent the cbmem console from writing to itself. BUG=b:213828947 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3fe0f666e2e15c88b4568377923ad447c3ecf27e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* src: Remove unused <cbfs.h>Elyes HAOUAS2022-01-175-5/+0
| | | | | | | | | | | Found using: diff <(git grep -l '<cbfs.h>' -- src/) <(git grep -l 'cbfs_allocator_t\|cbfs_load\|cbfs_ro_load\|cbfs_type_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_preload\|cbfs_unmap\|cbfs_prog_stage_load\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_type\|cbfs_file_exists\|cbfs_ro_file_exists\|mem_pool\|cbfs_cache\|cbfs_boot_device\|cbfs_boot_device_find_mcache\|cbfs_boot_device\|cbfs_get_boot_device\|cbfs_init_boot_device\|cbfs_boot_lookup\|cbfs_alloc\|cbfs_unverified_area_alloc\|cbfs_default_allocator_arg\|cbfs_default_allocator\|cbfs_cbmem_allocator\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_load\|cbfs_type_load\|cbfs_ro_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_file_exists\|cbfs_ro_file_exists\|cbfs_mdata\|cbfs_find_attr\|cbfs_file_hash' -- src/)|grep "<" Change-Id: Ib4dca6da1eb66bbba5b6e94fd623f4fcfc2f0741 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/i2c/tpm/Kconfig: Reduce visibility of some configsArthur Heymans2022-01-171-2/+2
| | | | | | | | | | | | I2C bus and address of the TPM are typically fixed on hardware so there is no need to be able to configure this in menuconfig. Change-Id: I1b6afa68fe753fb76348e0461209d218b14df7cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* oprom/yabel/io.c: Fix building for ENV_X86_64Arthur Heymans2022-01-171-2/+2
| | | | | | | | | | | Unknown if yabel works for X86_64 but now it builds. Change-Id: Iacdb9fde91a992b5010120f5824383ca4aebdd1a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* oprom/realmode/x86.c: Fix building for ENV_X86_64Arthur Heymans2022-01-171-2/+8
| | | | | | | | | | | Not tested on hardware. Change-Id: I8ce8d56da326aeff5ff9b400ded02d4309372519 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/common/cse: Add helper API for CSE SPI Protection ModeSubrata Banik2022-01-162-0/+22
| | | | | | | | | | | | | | | | | | | This patch checks if CSE's spi protection mode is protected or unprotected. Returns true if CSE's spi protection mode is protected, otherwise false. BUG=b:211954778 TEST=Able to build and boot brya with this change. Calling `cse_is_hfs1_spi_protected()` in coreboot is able to provide the SPI protection status. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I23f1a1c4b55d8da6e6fd0cf84bef86f49ce80cca Reviewed-on: https://review.coreboot.org/c/coreboot/+/60403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-1637-37/+48
| | | | | | | | | | | | | | | | | | | | | List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Abstract the sideband accessJohn Zhao2022-01-164-6/+9
| | | | | | | | | | | | | | | | The existing Sideband access is with the PCH P2SB. There will be future platforms which access the TCSS registers through SBI other than the PCH P2SB. This change abstracts the SBI with common API. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia6201762fe92801ce6b4ed97d0eac23ac71ccd37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/denverton_ns: Add the Primary to Sideband Bridge definitionJohn Zhao2022-01-161-0/+1
| | | | | | | | | | | | | | | | This change adds the Primary to Sideband Bridge(B0, D31, F1) definition for the platform in order to maintain the common block API build. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* arch/x86/spinlock.h: Support systems with >128 coresArthur Heymans2022-01-151-4/+4
| | | | | | | | | | | | | | | | | Each time the spinlock is acquired a byte is decreased and then the sign of the byte is checked. If there are more than 128 cores the sign check will overflow. An easy fix is to increase the word size of the spinlock acquiring and releasing. TEST: See that serialized SMM relocation is still serialized on systems with >128 cores. Change-Id: I76afaa60669335090743d99381280e74aa9fb5b1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60539 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/redrix{4es}: Add host device event supportWisley Chen2022-01-142-0/+74
| | | | | | | | | | | | | | Adding this host event to the EC SCI event and wake masks allows the system to generate an SCI and/or wake when this event happens. BUG=b:206012072 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I4f48244a4fca750a9de2ecc20f24786034d45b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix{4es}: Set tcc_offset value to 3Wisley Chen2022-01-142-0/+2
| | | | | | | | | | | | | | | | The redrix thermal team has determined that the TCC circuit trip temperature should be set to 97C, therefore, because the offset is subtracted from 100C, set the `tcc_offset` register in the devicetree to 3. BUG=b:200134784 TEST=build and verified by thermal team Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ifb63d63bc741b2a402328f256b43bc83e0a88a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/anahera{4es}: Set tcc_offset value to 3Wisley Chen2022-01-142-0/+2
| | | | | | | | | | | | | | | | The anahera thermal team has determined that the TCC circuit trip temperature should be set to 97C, therefore, because the offset is subtracted from 100C, set the `tcc_offset` register in the devicetree to 3. BUG=b:214088543 TEST=build and verified by thermal team Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I25b8a3d9e5fe28e9497b735c50a09994092b2243 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/felwinter: Update USB Type-C PLDEric Lai2022-01-141-4/+4
| | | | | | | | | | | | | | | | | After kernel change landed on Chromium tree. https://lore.kernel.org/r/20210407065555.88110-5-heikki.krogerus@linux.intel.com USB driver will use PLD to match the Type-C port. PLD needs to start from 1. BUG=b:214460183 TEST=boot into OS without kernel panic. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1493e46f8881b2f688f41f32755d4cf5a87e7656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/felwinter: Update audio_amp fw config field nameEric Lai2022-01-141-2/+2
| | | | | | | | | | | | | | | https://github.com/thesofproject/linux/pull/3271 Felwinter will use the OEM string for SOF tplg loading. Update the name that match to the kernel driver. BUG=b:210061842 TEST=dmidecode can show AUDIO_AMP-MAX98360_ALC5682VS_I2S_2WAY. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib6114d047762ba26071c9cdc6c43d80f933c1eb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61070 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya0: Enable CNVi DDR RFIM for brya0 variantRonak Kanabar2022-01-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | DDR interfaces emit electromagnetic radiation which can couple to the antennas of various radios that are integrated in the system, and cause radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for brya0 variant. Refer to Intel doc:640438 and doc:690608 for more details. BUG=b:201724512 BRANCH=None TEST=Build and boot with debug FSP and verify CnviDdrRfim UPD value. Change-Id: I6ad826d0039e400f219c2d407c51762c1751a909 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/brya: move SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES to commonEric Lai2022-01-142-11/+1
| | | | | | | | | | | | | | ADL support USB4/TBT. Select it will reserve PCI buses and hotplug mem and prefetch mem. BUG=b:206739931 TEST=build PASS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1171981c1318c2ecb65ba7959c4de9b5e179514e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60885 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-144-12/+4
| | | | | | | | | | | | | | | | List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-1411-34/+6
| | | | | | | | | | | | | | | | List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/brya/var/agah: update overridetreeTony Huang2022-01-142-1/+288
| | | | | | | | | | | | | Init basic override devicetree based on initial schematics BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: I7b7badacce27dd7da4f138c6f2465af518715e7f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60837 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: factor out eSPI SPI2 pads configuration functionsFelix Held2022-01-144-21/+41
| | | | | | | | | | | | | | verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses some of the registers directly. BUG=b:183149183 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner2022-01-1414-0/+28
| | | | | | | | | | | | | Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/tgl: deduplicate the PCIe root port mapMichael Niewöhner2022-01-141-17/+2
| | | | | | | | | | | | Make use of the helper introduced in the parent change to deduplicate the PCIe root port table. Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/tgl/pcie_rp: add TGL-H supportMichael Niewöhner2022-01-142-1/+21
| | | | | | | | | | | Add TGL-H support for the recently introduced code for differentiating CPU and PCH root ports by adding the missing TGL-H port map. Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* src/{drivers,lib}: Remove unused <console/console.h>Elyes HAOUAS2022-01-142-2/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ifad13ef418db204cf132fe00f75c6e66cd2bc51b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/brya: Adjust CSE RO and Data partition in the CSE regionSridhar Siricilla2022-01-131-2/+2
| | | | | | | | | | | | | | | | | | The patch adjusts CSE region's internal partitions' (CSE RO and Data partition) sizes to match with sizes of MFIT generated CSE Region's internal partitions. BUG=b:213993778 TEST=Generate coreboot for Brya and verify with MFIT generated coreboot. Cq-Depend: chrome-internal:4452789 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I5418c02f83134814e3f9959ee8c8da32ce8c7bec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60951 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Variants with ESx SoC use NEM for CARSubrata Banik2022-01-131-2/+2
| | | | | | | | | | | | | | | | | This patch ensures all brya variants with Alder Lake ESx SoC are using NEM by default for CAR set up. Default CAR configuration for QS SoC is eNEM. BUG=b:168820083 TEST=Able to build and boot brya0 variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib04bec188bdfde67c408fcd6b0603a5c2fb0fc97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/amd/*/chip.h: add missing gpio.h includeFelix Held2022-01-133-0/+3
| | | | | | | | | | | | | | Since we need the GPIO defines in the devicetree settings, include gpio.h in each SoC's chip.h file which will indirectly include the soc-specific soc/gpio.h header instead of having it indirectly included via soc/i2c.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id26721a6b8ae94784d4a90d7ccac28fef2be36dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro2022-01-134-104/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2511_04 Previous FSP version was v2471_02 Changes include: - UPDs description update in FspsUpd.h and FspmUpd.h - Adjust UPD Offset in FspmUpd.h - Name change of UPDs in FspmUpd.h and FspsUpd.h - Copyright year is updated in FspmUpd.h and FspsUpd.h - Updated spd_upds and dq_upds structure variables in meminit.c - Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask in fsp_params.c BUG=b:213959910 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4448696, chrome-internal:4445910 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: I39646c6812afbf622171361b8206daeacdaafac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/felwinter: Update ELAN touch HIDEric Lai2022-01-131-1/+1
| | | | | | | | | | | | | Per customer spec, change ELAN touch HID from ELAN9050 to ELAN9008. BUG=b:214010928 TEST=touch screen is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia95fdb378aaf241e38c0beb8ec392d57d77dc4db Reviewed-on: https://review.coreboot.org/c/coreboot/+/61027 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Fix include guard naming for emi.hYu-Ping Wu2022-01-131-3/+3
| | | | | | | | | | | | | | | | | Fix the name of the include guard for soc/mediatek/common/include/soc/emi.h. BUG=none TEST=emerge-corsola coreboot BRANCH=none Change-Id: Iddac3467959545b7db141545aaa2a135536f44f1 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Xi Chen <xixi.chen@mediatek.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
* console/cbmem_console: Rename cbmem_dump_consoleRaul E Rangel2022-01-133-3/+3
| | | | | | | | | | | | | | This function actually dumps cbmem to the UART. This change renames the function to make that clear. BUG=b:213828947 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icc314c530125e5303a06b92aab48c1e1122fd18c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/var/taeko: Modify power sequence for SSD deviceKevin Chang2022-01-122-10/+32
| | | | | | | | | | | | | | | | In order to avoid having the FSP fail to detect the SSD device downstream of the RP, its PERST# must be deasserted earlier in the boot flow, therefore move PERST# deassertion to a romstage GPIO table. BUG=b:213828931 TEST=Build FW and run stress exceed 1000 cycles. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I4e5eed7db16e1420ccbc22a5c30b00bedd190a2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common/gpio: Fix cosmetic issue with `gpio_lock_pads`Subrata Banik2022-01-121-3/+4
| | | | | | | | | | | | | | | | This patch replaces hardcoded `4` (next offset Tx state) with `sizeof(uint32_t)` for calculating 'Tx state offset'. Also, add checks to detect the specific GPIO lock action between `LOCK_CONFIG` or 'LOCK_TX'. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iff712b16808e0bc99c575bb2426a4f84b89fdb73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* sc7180: Update video mode active horizontal/vertical/total calculationsVinod Polimera2022-01-121-13/+6
| | | | | | | | | | | Remove vbp & hbp as the names are misleading and use edid variables to simplify the video mode active and total calculations. Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/glados/variants/sentry: Increase CPU critical temp threshold to 105CSumeet Pawnikar2022-01-121-1/+1
| | | | | | | | | | | | | | | | | | | | | During certain kind of test scenario, observed that CPU temperature spikes till 98C and based on current thermal critical policy temperature threshold of CPU set to 98C, it initiates the system wide abrupt shutdown. To avoid this kind of abrupt system shutdown, update cpu critical temperature threshold from 98C to 105C. BUG=b:213476881 BRANCH=glados TEST=Built and booted on glados Change-Id: I56df9285b3c247866a5bfa6dc59d1856544de41c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-15 11:27:18 +0000