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* soc/amd/cezanne/fch: process ACPI PM/GPE and GPIO eventsFelix Held2021-04-141-0/+6
| | | | | | | | | | BUG=b:184549804 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ebbe9667d18a96b1a363d0353c612e214699d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52273 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: save chipset state to CBMEMMartin Roth2021-04-142-0/+5
| | | | | | | | | | | | | | | Guybrush complains that this is missing during the boot, so add it to cezanne. I verified that the registers in gpio.c are correct. BUG=b:184549804 TEST=Build and boot Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/picasso/romstage: factor out chipset state saving functionalityFelix Held2021-04-146-23/+41
| | | | | | | | | | | | Since Cezanne needs the exact same code, move it to the common directory and add a Kconfig option to add this functionality to the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/clevo/cml-u: drop LPC generic range for port 80Michael Niewöhner2021-04-131-5/+3
| | | | | | | | | | | | Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entry from clevo/cml-u, which has been forgotten in commit c5f1dc9. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I05844db4cfe96e6075bd6526ffc242973a2082c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/hp/280_g2/romstage.c: Correct CaVrefConfig settingAngel Pons2021-04-131-1/+1
| | | | | | | | | | With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1. Change-Id: I64606824b4f82affb0fcfc78e68ba29859a1cc69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* dptf: Move platform-specific information to `struct dptf_platform_info`Tim Wawrzynczak2021-04-1312-45/+107
| | | | | | | | | | | | | DPTF HIDs are different per-platform going forward, so refactor these into SoC-specific structures which the DPTF driver can query at runtime for platform-specific information. Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoCYidi Lin2021-04-1311-0/+302
| | | | | | | | | | TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* nb/intel/x4x: Refactor sync DLL programming (part 2)Nico Huber2021-04-121-41/+39
| | | | | | | | | | | | | | | | | | | Instead of counting consecutive matches (in `j`), check for a second match directly in the control flow. Also, add some dedicated variables: * `tap`: Keeps track of the tap value that resulted in a match and is eventually programmed into the hardware. * `tap2`: Is just temporarily used to search for another edge. Keeping `tap` sync'ed with the hardware has the benefit that we don't need to read the programmed value back for later fixups. Change-Id: I3ae541c39efdc695f5ca74bc757b2f009239ec93 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/x4x: Refactor sync DLL programming (part 1)Nico Huber2021-04-121-30/+32
| | | | | | | | | | | Extract some common code patterns into functions. Change-Id: I5f8d40bb55d4b4f0639e0287881ae0ecde298590 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* nb/intel/x4x: Sort code in program_dll()Nico Huber2021-04-121-16/+16
| | | | | | | | | | | | Move the last block of the sync DLL programming up. It's independent of the switch/case statement that it's moved around. Change-Id: I71bc1ca1c629e4f2f4a13474c7e2c22d1a3b65d9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/mancomb: Temporary fix to set eSPI muxEric Lai2021-04-121-0/+22
| | | | | | | | | | | BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ief59bdea392ab3f141ccf7444c608aef99701d2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* chromeec: make ssfc optional in fw_configKangheui Won2021-04-121-4/+2
| | | | | | | | | | | | | | | | | | | When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is not set, all fw_config is invalidated. But for some platform this may not be necessary, we can treat missing SSFC as zero and use other 32 bits of firmware config. BUG=b:184809649 TEST=boot and check fw_config is not -1 even if ssfc is not set BRANCH=zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I21c7b0d449a694d28ad7b3f14b035e3a5830030a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/*: drop LPC generic range for port 80Michael Niewöhner2021-04-1211-26/+14
| | | | | | | | | | | Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/amd/majolica/port_descriptor: use GPIO number defineFelix Held2021-04-121-1/+2
| | | | | | | | | | TEST=Timeless build results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie39dc99bef4eb3776388d7406239bac6031bfaaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/52193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/mancomb: add DXIO and DDI descriptorsEric Lai2021-04-121-0/+97
| | | | | | | | | | | | | Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/amd/bilby: Use Picasso VBIOS as defaultRitul Guru2021-04-121-1/+1
| | | | | | | | | | | use PicassoGenericVbios.bin as default instead of raven VBIOS for Bilby. Change-Id: I99621173a33a1154f8bb4929d199288265bbe04d Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52209 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Enable HECIAseda Aboagye2021-04-111-0/+3
| | | | | | | | | | | | | | | | This commit enables HECI such that interface can be used from userspace on the dedede mainboards. BUG=b:184219504 TEST=Build and flash drawcia, verify that Intel Flash Programming Tool can communicate with the Converged Security Engine. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I5b28c471d6554a5e14538073d48ef47da05936fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/common/block/gpio: remove SoC type check in gpio_fill_wake_stateFelix Held2021-04-111-4/+0
| | | | | | | | | | | | | | | | | | Verified that all accessed registers exist in all SoCs that use this code (Carrizo, Mullins, Stoneyridge, Picasso and Cezanne at the moment) and that the bit definitions match as well. Also at the time of writing this patch only Picasso calls gpio_fill_wake_state, so dropping the check won't change behavior. This also avoids having SoC specific code that doesn't get selected by Kconfig options in the common AMD SoC directory and also avoids having to add a check for SOC_AMD_CEZANNE to support this functionality on Cezanne in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If770780a67776daf81744db1b635ffd402653a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52223 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/amd/pi/hudson: remove unused Bolton PI FCH codeFelix Held2021-04-118-49/+2
| | | | | | | | | | | | | | | | | | There is no nb/amd/pi northbridge left in coreboot that could be paired with the Bolton FCH, since the remaining nb/amd/pi northbridges all use an integrated FCH (Avalon on Mullins and Kern on Carrizo) while Bolton is a discrete FCH. I ran into this when verifying if the common soc/amd GPIO functionality that gets added by selecting SOC_AMD_COMMON_BLOCK_BANKED_GPIOS is valid for all chips selecting it and that code isn't valid for Bolton that uses the old GPIO 100 interface. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iffe876bee96e42645e1be10730b78959b1c06d59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork/vilboz: Update register parameters for sx9324 tuningFrank Wu2021-04-111-9/+17
| | | | | | | | | | | | | | To update the sx9324 registers after RF team fine-tuned the parameters. BUG=b:172397658 BRANCH=firmware-zork-13434.B TEST=build coreboot and verify the sx9324 function Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ief85bc61952144a1d7a151100d89938517078ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51936 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spd.h: Move `DIMMx` macros to i440bx/raminit.hAngel Pons2021-04-112-10/+6
| | | | | | | | | | These macros aren't needed anywhere else, so reduce their visibility. Change-Id: Ie8d14849b4fb86d34a841d4a13ee3bbb46f9f71c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52061 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/x/smbus.c: Correct register access widthAngel Pons2021-04-113-14/+3
| | | | | | | | | | The register is 16 bits wide. Change-Id: I58d44a17613965e0a27aab5246dcdce68e1a8201 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/prodrive/hermes: Fix eeprom readingArthur Heymans2021-04-101-4/+3
| | | | | | | | | | | | | The logic for bytes to copy to the function input pointer was wrong. What it did was to loop over all 2 bytes that need to be read and only copy the first byte. Change-Id: Ic08cf01d800babd4a9176dfb2337411b789040f3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* mb/intel/shadowmountain: Enable Bluetooth config in the devicetreeSridhar Siricilla2021-04-101-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | The patch enables Bluetooth config in the devicetree and removes non-existent Bluetooth PCI interface. TEST=Verified by checking Garfield Peak controller's PID:VID(8087:0033) in the lsusb ouput. Output of lsusb: Bus 004 Device 003: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN Bus 004 Device 002: ID 0bda:0411 Realtek Semiconductor Corp. 4-Port USB 3.0 Hub Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 003 Device 003: ID 0781:55a9 SanDisk Corp. Dual Drive Bus 003 Device 004: ID 413c:2113 Dell Computer Corp. Dell KB216 Wired Keyboard Bus 003 Device 002: ID 0bda:5411 Realtek Semiconductor Corp. 4-Port USB 2.0 Hub Bus 003 Device 005: ID 8087:0033 Intel Corp. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I7a54d344ef1b0418bee56e7308977a61604b954a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52182 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Set Power state after power failureKarthikeyan Ramasubramanian2021-04-102-1/+4
| | | | | | | | | | | | | | | | | | Configure the power state to return to when the power is re-applied after power failure. BUG=b:183739671 TEST=Build and Boot to OS in Majolica and Guybrush. By default when the power fails the device turns on after power is re-applied. When the POWER_ON_AFTER_POWER_FAILURE is disabled, the device remains off even after the power is re-applied. Change-Id: I21c5da08c82156d6239450ef6921771da74cbaa1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52049 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common: Handle power resume after power failureKarthikeyan Ramasubramanian2021-04-104-0/+77
| | | | | | | | | | | | | | | Introduce a power management library to handle the power resume after power failure. Enable HAVE_POWER_STATE_AFTER_FAILURE config when this library is enabled. BUG=b:183739671 TEST=Build Guybrush and Majolica mainboard. Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/cezanne: Add GRXS and GTXS methodEric Lai2021-04-106-47/+58
| | | | | | | | | | Add GRXS and GTXS support. Move the gpio method into common place. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/brya: Change GPP_E16 default to highAlex Levin2021-04-101-1/+1
| | | | | | | | | | | | | | To enable WWAN we want to release it from reset start. BUG=b:180166408 TEST=WWAN enumerates on brya Change-Id: I4f9884d3b2fc8822dda1a6fe743c863aa6c696da Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52199 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Drop unreferenced `InternalGfx`Angel Pons2021-04-101-1/+0
| | | | | | | | | | This option is not referenced anywhere. Drop it. Change-Id: Ie59de5399a9b1713109bf334d4ad1d7f7efb91f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52104 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/haswell: Use new fixed BAR accessorsAngel Pons2021-04-101-16/+16
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I5fb31f88bbf7c2f1e44924ca2d3169257a9598dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/dell/optiplex_9010: Use new fixed BAR accessorsAngel Pons2021-04-101-1/+1
| | | | | | | | Change-Id: I4d949d252ca24ebd4e4ed9c7dd17ede3810a8bfd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/intel/i945: Use new fixed BAR accessorsAngel Pons2021-04-105-381/+380
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: Ifea441ad95293ad93d11a5f2521370cfd387289b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/intel/gm45: Use new fixed BAR accessorsAngel Pons2021-04-1012-609/+598
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I18f40d1bc3172b3c1b6b4828cefdb91aea679ba2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51880 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/gm45/gm45.h: Guard `CxDRC1_NOTPOP` macro parametersAngel Pons2021-04-101-1/+1
| | | | | | | | | | | | | Wrap `r` in parentheses to avoid unexpected behavior with compound expressions. Fortunately, all uses of this macro do not cause issues. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Id0f05a507c5e7e8c50e9765261d86bae73c7b5a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/intel/x4x: Use new fixed BAR accessorsAngel Pons2021-04-106-500/+484
| | | | | | | | | | | | Some cases break reproducibility if refactored, and are left as-is. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I163995c0b107860449c2f36ad63e4e4ca52decb2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51878 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x: Correct and use macros for CLKCFGAngel Pons2021-04-104-6/+7
| | | | | | | | | | | | | The `CLKCFG_UPDATE` macro is copied from gm45 and unused. Correct it and use the CLKCFG macros instead of magic values. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I17e972eba21282ac84c7afe10b7149cd1131fd07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51877 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x/dq_dqs.c: Avoid breaking strings over multiple linesAngel Pons2021-04-101-17/+11
| | | | | | | | | | | Breaking strings across multiple lines hurts greppability. Refactor the code a bit to drop one indentation level, and then reflow the strings. Change-Id: I0accdfd0d2c5f58e4da493ba0d4b5c6a067d92c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51876 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x: Add missing newlines to log messageAngel Pons2021-04-101-2/+2
| | | | | | | | Change-Id: I67f38bcb1ec0fbbfb7f2f3fcfaf2f9bf2d9ac92c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51875 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x: Reflow long linesAngel Pons2021-04-106-254/+133
| | | | | | | | | | | | Try to unbreak long lines and user-visible strings. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I1bbf08cf665157840380517302ca581718e3cbe4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51874 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x/dq_dqs.c: Fix typo in variable nameAngel Pons2021-04-101-3/+3
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I143e69446614ddc80562e5931c260329257fd3cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51873 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/x4x: Correct sync DLL phase searchAngel Pons2021-04-101-1/+1
| | | | | | | | | | Bit 4 needs to be set then polled for after changing sync DLL taps. Change-Id: I61b73998dec84710eec0d2561a6f4d88068e3373 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51872 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/pineview: Replace remaining BAR accessorsAngel Pons2021-04-101-12/+10
| | | | | | | | | | These changes are not reproducible for some reason. Change-Id: If1fcd0285c3a14686f7deb70d83a4c63d57d62fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51871 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/pineview: Use new fixed BAR accessorsAngel Pons2021-04-103-477/+478
| | | | | | | | | | | | Some cases break reproducibility if refactored, and are left as-is. Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: I484f04455fe4baa69888645554fcd72881ba197d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51869 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/ironlake: Use new fixed BAR accessorsAngel Pons2021-04-104-660/+646
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Ia0a086bd28b796d2cbe1c7a056922721c95612b8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51868 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel: Replace remaining BAR accessorsAngel Pons2021-04-102-24/+5
| | | | | | | | | | These changes are not reproducible for some reason. Change-Id: I43b445b8af8871db87fb86747db8a35cec75716a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51867 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/sandybridge: Use new fixed BAR accessorsAngel Pons2021-04-1012-336/+320
| | | | | | | | | | | | One instance in northbridge.c breaks reproduciblity when changed. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I2148183827bcacc9e6edb91b26ad35eb2dae5090 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51866 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/haswell: Use new fixed BAR accessorsAngel Pons2021-04-104-98/+70
| | | | | | | | | | | | | There are some cases in `northbridge_topology_init` where condensing the operation using one macro changes the binary, and have been left as-is. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I59c7d1f8d816b95e86d39dcbf7bc7ce8c34f0770 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51865 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/common/fixed_bars.h: Add new read/write accessorsAngel Pons2021-04-101-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | The {MCH,DMI,EP}BAR macros can be used for both reading and writing. While this can sometimes be useful, compile-time overflow checking is limited. Moreover, and-masks need to be bit-wise negated, which is easy to forget and may result in spurious overflow warnings, and silencing them with a cast also suppresses true integer overflow issues. To address these limitations and for consistency with the existing MMIO API (arch/mmio.h and device/mmio.h), these macros will be replaced with prefixed wrappers around MMIO API functions. However, existing platform code needs to be refactored, and the risk of introducing regressions is substantial. To minimize the risk of breakage, the bulk of the platform code changes will be verified using reproducible builds. This patch introduces the new accessors, to be put to use in follow-ups. These accessors are implemented as macros so that subsequent commits can be verified using reproducible builds. They will be replaced with actual functions after refactoring all platforms. Change-Id: I85376a9e2f6cd042b41036f90de7f9edc7ad4508 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51864 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel: Factor out remaining MCHBAR macrosAngel Pons2021-04-106-49/+10
| | | | | | | | | | Except for some formatting differences, the macros are equivalent. Change-Id: I5dc4f115b0873fb96683263ecd152d3d1504647d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51863 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Skip D3Cold for TBTSubrata Banik2021-04-101-0/+6
| | | | | | | | | | | | | | | | | | | Check TBT NVM FW Ready (INFR) bit to skip D3Cold for TBT when device is in disconnected state. Not adhering this recommendation is blocking the S0ix state transition. BUG=b:183670327 TEST=S0ix state transition occurs with TBT disconnected. Change-Id: Ib9b9ceee4393aeba37fdcb4e05d1b279a6ff72d2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 22:00:21 +0000