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* mb/google/brya/var/agah: Explicitly program GPP_H13 in ramstageTim Wawrzynczak2022-09-261-0/+2
| | | | | | | | | | | | | | | In order that GPP_H13 not use the GPIO override programming from its baseboard (brya), explicitly program GPP_H13 to a output HIGH instead of relying on the 20K pullup from the baseboard. BUG=b:240617195 TEST=SSD still functional Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iddedebe2d5cfc0123932b14980d1268bcb147703 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/google/brya/var/agah: Update PEXVDD enable GPIO for next board revTim Wawrzynczak2022-09-263-20/+49
| | | | | | | | | | | | | | | | | The next rev of this board will move the dGPU PEXVDD enable pin from GPP_E10 to GPP_F12. This patch handles both the old and newer revisions by using an ACPI Name to hold the GPIO # for PEXVDD enable. It also cleans up the GPIO handling a little bit between board revs. BUG=b:242752623 TEST=dGPU is functional and power sequencing tests still pass on board rev 2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icc7968777f86ab07561b0a861b7d22ec714d1c34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/google/brya/var/banshee: Remove privacy_gpioRicardo Ribalda2022-09-261-1/+0
| | | | | | | | | | | | | | | | | | | On Banshee, when the privacy switch is toggled the camera is disconnected. Which means that we will never be able to tell the user that the privacy switch is enabled when the camera is on, making the virtual control unusable. Remove the description. BUG=b:248219472 BRANCH=firmware-brya-14505.B TEST=none Change-Id: I1a241bd889c0c1aae039510a0620748b2f7a6806 Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/skyrim/var/winterhold: Bug fix, modify GXTP7863 irq settingEricKY Cheng2022-09-262-2/+2
| | | | | | | | | | | | | Modify GXTP7863 generic.irq to generic.irq_gpio. BUG=b:245082617 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Iaf6cc6010132d5b33b06909ceb1069115a911b48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3361_03Selma Bensaid2022-09-262-240/+261
| | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v3361.03 In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:247855492 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: I267a0aefca18492bcbcfbf7acbe271887f0a39cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* soc/mediatek/mt8186: Allow SCP to access H264 encoderRunyang Chen2022-09-261-1/+1
| | | | | | | | | | | | | | | | | | | Issue: Camera APP is not functional after CB:67434 applied. Root cause and solution: SCP hardware needs to access H264 encoder registers, so we need to remove the DEVAPC protection of H264 encoder for SCP. BUG=b:247743696 TEST=camera APP is functional. Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: I95946346018bff6a8f2dc02b1ff3e24ad079fc90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67787 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* Revert "mb/google/rex: Create 64MB AP Firmware binary for Proto 0"Subrata Banik2022-09-261-3/+1
| | | | | | | | | | | | | | This reverts commit 1a8eb6c02103727431ac1ea23f4f507e49f3cde7. Reason for revert: migrating to the 32MB AP Firmware hence, need to revert this CL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibea1ad0cff008f9391cbda9e51899557b1e9c979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* cpu/x86/smm/smihandler: use lapicid()Felix Held2022-09-241-6/+2
| | | | | | | | | | | | | | | Replace nodeid() function in cpu/x86/smm/smihandler.c with calling lapicid() from include/cpu/x86/lapic.h. TEST=Timeless build for lenovo/g505s which includes this file in the build results in identical firmware image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I336ca9888e24e4d6f10a81cc4f3760c9d7c8f4bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* cpu/x86/mp_init: drop unused MAX_APIC_IDS defineFelix Held2022-09-241-2/+0
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I599e26a40ab584232614440612e95c91a698df27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* include/cpu/x86/mtrr: define NUM_FIXED_MTRRS once in mtrr.hFelix Held2022-09-243-2/+1
| | | | | | | | | | | | | | | | Instead of defining NUM_FIXED_MTRRS in both cpu/x86/mp_init.h and cpu/x86/mtrr/mtrr.c in two different ways that will evaluate to the same value, define it once in include/cpu/x86/mtrr.h which is included in both C files. TEST=Timeless build for amd/mandolin results in identical firmware image Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71cec61e22f5ce76baef21344c7427be29f193f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* drivers/mrc_cache: Compare hashes instead of full dataReka Norman2022-09-241-32/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current MRC cache update process is slow (28 ms on nissa), because cbmem is not cached in romstage. Specifically, the new MRC data returned by the FSP is stored in the FSP reserved memory in cbmem, so operations on the new data (computing the checksum, comparing to the old data) are slow. Replace the data checksum in the MRC header with a hash, and compare hashes instead of comparing the full data. This has two benefits: 1. The xxhash function is faster than computing an IP checksum (4 ms vs 14 ms on uncached data on nissa). 2. There's no need to memcmp() the full MRC data, which takes 14 ms on nissa. Before: 550:starting to load ChromeOS VPD 867,930 (4,664) 3:after RAM initialization 896,020 (28,090) 4:end of romstage 906,274 (10,254) After: 550:starting to load ChromeOS VPD 864,820 (4,649) 3:after RAM initialization 869,652 (4,831) 4:end of romstage 879,909 (10,257) BUG=b:242667207 TEST=Check that MRC caching still works as expected on nissa. Corrupt the MRC cache and check that memory is retrained. Change-Id: I1b7848d1d05e555b61e0f1cb605550dfe3449c6d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67670 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/fsp_relocate: add PE32 section supportEddie Vas2022-09-241-39/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently published Intel CedarIslandFSP binary contains PE images in FSP-M and FSP-S. This causes coreboot boot hang on DeltaLake servers. PI spec PI_Spec_1_7_final_Jan_2019 on uefi.org talks about FV files requiring to support SECTION_PE32 sections and FSP specification states that FSP images are created in alignment with PI specification. FSP images are relocated at build time and run time using the func fsp_component_relocate. That code only supported TE image relocation so far. The change required to add support for pe_relocate in fsp-relocate.c I had to move a few functions to top of file as they need to be used by pe_relocate but were placed below the te_relocate function. I chose to place pe_relocate function next to te_relocate. The code supports PE32 format, not PE32+, at this time. Links for PE and FSP specs are provided below for reference. Link= https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf Link= https://uefi.org/sites/default/files/resources/PI_Spec_1_7_final_Jan_2019.pdf TESTED= This code is tested with FSP version 33A for DeltaLake boot which has FSP-M and FSP-S as PE32 sections. This FSP version does not boot on DeltaLake without this change. Change-Id: I01e2c123d74f735a647b994aa66419c9796f193e Signed-off-by: Eddie Sharma <aeddiesharma@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nathaniel L Desimone <nathaniel.l.desimone@intel.com>
* cpu/x86/smm/smihandler: use existing LAPIC ID register definitionFelix Held2022-09-231-2/+2
| | | | | | | | | | | | | | Instead of redefining the register address in smihandler.c, use the existing definitions from include/cpu/x86/lapic_def.h. TEST=Timeless build for lenovo/g505s which includes this file in the build results in identical firmware image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id22f9b5ce53c7bced6bbcc3f5026d4c793b34f78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67776 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/timer_queue.c: Fix function signatureFred Reitberger2022-09-231-1/+1
| | | | | | | | | | | | | | | | | | The timer_sched_callback function signature was changed in timer.h as part of commit d522f38c7bfccdc4af71bcad133aec20096f3f6c (timer: Change timer util functions to 64-bit) but the implementation was not updated to match. TEST=Enable timer queue and build Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie00b027790131f42bd79fbc6ea400a056e67949b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67767 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src/mb/skyrim: Rename Sabrina to MendocinoJon Murphy2022-09-233-9/+9
| | | | | | | | | | | | | | | | | 'Mendocino' was an embargoed name and could previously not be used. Update references for consistency with the correct naming convention. BUG=b:245727030 TEST=builds and boots to kernel Cq-Depend: chrome-internal:4878294 Cq-Depend: chromium:3763392 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic0248a872dfc92486658aa9bd92bed755dbf59d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67750 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/mendocino: Add svc_set_fw_hash_tableKarthikeyan Ramasubramanian2022-09-233-0/+45
| | | | | | | | | | | | | | | | | | Add new PSP svc call to pass psp firmware hash table to the PSP. psp_verstage will verify hash table and then pass them to the PSP. The PSP will check if signed firmware contents match these hashes. This will prevent anyone replacing signed firmware in the RW region. BUG=b:203597980 TEST=Build and boot to OS in Skyrim. Change-Id: I512d359967eae925098973e90250111d6f59dd39 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67259 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/{google,intel}/*/ec: Decrease loglevel of init messages to BIOS_INFOElyes Haouas2022-09-236-6/+6
| | | | | | | | | | | | | BIOS_ERR is inappropriate since the init message is informational. Use BIOS_INFO instead. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6fc15291a6d177a1b9e258d08e165224e5e10b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67733 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/brask/variants/moli: update emmc_rtd3 enable gpio pinRaihow Shi2022-09-231-0/+15
| | | | | | | | | | | | | EN_PP3300_EMMC has be changed to GPP_A21 for DP++ and it based on Moli GPIO Table_20220803.xlsx, so update enable_gpio for emmc_rtd3 by board_ver. BUG=b:241370405 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I129706861fd1fcf061371ce94352331ef44359d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/siemens/mc_apl7: Enable libgfxinit for the boardJan Samek2022-09-223-0/+17
| | | | | | | | | | | Add the gma-mainboard.ads for display output definition and enable the libgfxinit usage in mainboard Kconfig. Change-Id: I7e7a44736a8136b5320821e744134c7d64c7f1b4 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67683 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/common/lockdown: Guard sa_lock_pamSean Rhodes2022-09-222-1/+7
| | | | | | | | | | | | Guard sa_lock_pam with PAM0_REGISTER so it doesn't run on platforms that don't select this. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5055d09c634851e9f869ab0b67a7bcab130f928c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66492 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/pch: Add a block specific to Apollo LakeSean Rhodes2022-09-224-27/+41
| | | | | | | | | | | | | | | | Add SOC_INTEL_COMMON_PCH_CLIENT which is specific to Apollo Lake. This is used to select the options that Apollo Lake requires, without the ones specific to a PCH as Apollo Lake doesn't have a PCH. This change also enables SOC_INTEL_COMMON_PCH_LOCKDOWN for Apollo Lake. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I084a05f904a19f3b7e9a071636659670aa45bf3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/picasso: Add support for PSP NVRAM base addr and sizeRitul Guru2022-09-221-0/+10
| | | | | | | | Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I07d5aaac9c05986e8a952c7e670d002d864e18d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67170 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/agah: Explictly program the dGPU's PCI IRQTim Wawrzynczak2022-09-221-1/+17
| | | | | | | | | | | | | | | | | | | | | Currently the `pch_pirq_init()` function in lpc_lib.c will program PIRQ IRQs for all PCI devices discovered during enumeration. This may not be correct for all devices, and causes strange behavior with the Nvidia dGPU; it will start out with IRQ 11 and then after a suspend/resume cycle, it will get programmed back to 16, so the Linux kernel must be doing some IRQ sanitization at some point. To fix this anomaly, explicitly program the IRQ to 16 (which we know is what IRQ it will eventually take). BUG=b:243972575 TEST=`lspci -vvv -s1:00.0|grep IRQ` shows IRQ 16 is programmed at boot and stays consistent after suspend/resume. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I66ca3701c4c2fe5359621023b1fd45f8afd3b745 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67746 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/acpi: Don't clear GC6 flag after GC6 entryTim Wawrzynczak2022-09-221-2/+1
| | | | | | | | | | | | | | | | According to Nvidia, the GC6 flag (DFEN) should not get cleared after a successful GC6 entry; the kernel driver will not re-inform ACPI that the exit should be GC6 exit as well. BUG=b:243888246 BRANCH=brya TEST=tested by Nvidia Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I220795928d03f269de48278ea0ab57de7253fad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67745 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch: split up hatch and puff baseboardsMatt DeVillier2022-09-2292-177/+1604
| | | | | | | | | | | | | | | | | The hatch and puff baseboards have diverged enough to where it makes more sense to split them into separate boards. Copy the mb/google/hatch directory into a new dir 'puff' and strip out all boards and items related to the hatch baseboard. Remove all puff-related items from the original hatch directory. Clean up and alphabetize Kconfig selections. Test: build and boot akemi hatch variant and wyvern puff variant. Change-Id: I8c7350f3afcff3ddefc6fa14054a3f9257568cd3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62970 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* common/block/fast_spi: Add extended BIOS window as reserved regionWerner Zeh2022-09-222-5/+5
| | | | | | | | | | | | | | | | The fast SPI driver reports the BIOS window as reserved so that the OS is aware of this region. Now that platforms which supports an extended BIOS window are added to this driver, add the extended range as reserved as well if it is enabled. And since this is now handled in the SPI driver itself, remove the extended BIOS region reporting from common systemagent code. Change-Id: Ib5c735bffcb389be07c876d7b5b2d88c545a0b03 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driverWerner Zeh2022-09-2210-31/+15
| | | | | | | | | | | | | | | | | | | | | | | | There are two classes of SPI controllers on Intel chipsets: * generic usable SPI controllers * SPI controller hosting the BIOS flash (fast SPI controller) While the first class can be used for generic peripheral attachment the second class mostly controls the BIOS flash and a TPM device (if enabled). The generic SPI driver is not fully applicable to the fast SPI controller. In addition, the fast SPI controller reports the reserved MMIO range used for the BIOS flash mapping so that the OS is aware of this range. This patch moves the fast SPI controller of all known SoCs to the fast SPI driver in common code. In addition, the PCI device for the fast SPI controller is removed from the function 'spi_soc_devfn_to_bus' as this is a callback of the generic SPI driver. Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vc/intel/fsp/mtl: Update header files from 2304_01 to 2344_00Srinidhi N Kaushik2022-09-222-748/+708
| | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2344_00, previous version being 2304_01. FSPM: 1. Address offset changes FSPS: 1. Deprecated CstateLatencyControlTimeUnit UPDs 2. Deprecated HybridStorageMode 3.Address offset changes BUG=b:245167089 TEST=emerge-rex intel-mtlfsp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Iaee5c66811c340d12921ff9247461df36de4739a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/siemens/mc_apl7/Kconfig: Enable PTN3460 early initJan Samek2022-09-221-0/+4
| | | | | | | | | | | | | Enable early initialization of the PTN3460 DP-to-LVDS bridge on this board in order to allow showing the bootsplash screen at coreboot runtime. Change-Id: Ib1b727cef5fb8bea2d6d6c9896ad0107caeea51a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67682 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/i2c/ptn3460: Add early init optionJan Samek2022-09-222-0/+52
| | | | | | | | | | | | | | | | | | | | Create Kconfig options and boot state machine callback in ramstage for an early initialization of the PTN3460 DP-to-LVDS bridge. This allows showing the bootsplash screen on mainboards utilizing this chip during the PCI device enumeration. BUG=none TEST=Select PTN3460_EARLY_INIT config switch in mainboard Kconfig and check the log for "Attempting PTN3460 early init" message. If the board (e.g. siemens/mc_apl7 in this case) is also configured for showing the bootsplash logo, it should be now visible. Change-Id: I5424d062b3fb63c78cfced3971376353be11c504 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67681 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/cherry: Initialize PCIe by SKU encodingYu-Ping Wu2022-09-221-18/+21
| | | | | | | | | | | | | | | | | | | | | | All cherry boards (tomato, dojo) share the same SKU ID encoding, in the sense that a device has NVMe storage if and only if the BIT(1) of SKU ID is set (otherwise eMMC). Therefore, instead of hard coding the list of NVMe (PCIe) SKU IDs, we check the BIT(1) to decide whether to initialize PCIe. In addition, in preparation for UFS devices coming in the future, reserve BIT(3) (which is unset for all of current SKUs) for them. BUG=b:237953117, b:233327674 TEST=emerge-cherry coreboot BRANCH=cherry Change-Id: I9b30338645a87f29f96a249808b90f1ec16f82df Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* cpu/x86/smm/smm_module_loader.c: Fix STM setupEugene Myers2022-09-221-1/+1
| | | | | | | | | | | | | | | | | CB:63475 inadvertently disabled the STM by moving its load point off of the MSEG boundry, which is a hardware requirement. In addition, the BIOS resource list cannot be located within the MSEG. This patch fixes the issue by moving the STM load point to the MSEG boundry and placing the bios resource list just below the MSEG where the STM setup functions can find it. Fixes: commit 5747f6c (cpu/x86/smm_module_loader.c Rewrite setup) Signed-off-by: Eugene Myers <edmyers@tycho.nsa.gov> Change-Id: I7359939063bb1a172fcb701551c099edebfbedd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67665 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registersLiju-Clr Chen2022-09-222-0/+10
| | | | | | | | | | | | | | | | | | | This patch fixes AP hanging issue caused by the handshaking between MCUPM and CPUfreq driver. CPUfreq hardware failed to read MCUPM registers due to DEVAPC permission. Therefore, update the DEVAPC settings to fix this issue. BUG=none TEST=CPUfreq in kernel test pass. Change-Id: I6b30b01fc0be052182599709cbcc9139e6d09742 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67724 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/crota: set tcc_offset value to 1 ℃Johnny Li2022-09-211-0/+1
| | | | | | | | | | | | | | | | Set tcc_offset value to 1℃ in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:246913963 TEST=USE="project_crota project_brya" emerge-brya coreboot Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: Ie2f60bed34fbd6fa3624be60138511a22b199a8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/intel/meteorlake: Skip the TCSS D3 cold entry sequencezhaojohn2022-09-211-1/+7
| | | | | | | | | | | | | | | This patch provides a workaround which skips requesting IOM for D3 cold entry sequence. BUG=b:244082753 TEST=Verified MUX configuration after hot plugging Type-C devices on Rex and MTL RVP boards. Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown"Tim Wawrzynczak2022-09-201-8/+5
| | | | | | | | | | | | | This reverts commit 7ef5376123d4d0ebb811795fcee1de7066f65a0f. Reason for revert: It was merged before its dependencies so now master is broken. Change-Id: Ia270efaed4f5c9d0c7b9761ae22dec55f57f74cf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67285 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "Kconfig: Allow x86 to compress pre-ram stages if not run XIP"Martin L Roth2022-09-201-4/+4
| | | | | | | | | | | | This reverts commit 6317aff5b3028ad44b7885b6b63263c55b5aadb3. Reason for revert: fix broken tot master Change-Id: Ie8075cf6c80448bfc957a1e1183f0283d2011b1b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67287 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "mb/prodrive/hermes: Add part numbers to SMBIOS"Angel Pons2022-09-202-11/+1
| | | | | | | | | | | | | | | This reverts commit d6695626631a86d9613ea7c34ff0e898fbfa443c. Reason for revert: Was submitted out-of-order and with an unresolved TODO in the commit message. Change-Id: Id5a8770226afbfcdf63d451157e4586b6cdd5189 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67284 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/kbl: Correct USB port for BluetoothSean Rhodes2022-09-201-3/+3
| | | | | | | | | | | | Previously, the Bluetooth interface worked when port 9 was enabled. Now, it works with port 5 enabled, which matches the schematic. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If783e60c8120adcd6522676cb3343ed46bf39d78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/dedede: Resume from suspend on critical batteryIvan Chen2022-09-201-1/+5
| | | | | | | | | | | | | | | | | | | | | | This patch makes dedede EC wake up AP from s0ix when the state of charge drops to low_battery_shutdown_percent. Demonstrated as follows: 1. Boot OS. 2. Run powerd_dbus_suspend. 3. On EC, run battfake 4. 4. System resumes. BUG=b:244253629 TEST=Verified on dedede Change-Id: I39234d2b9e739383b5f96be49077f8c9831fa0fa Signed-off-by: Ivan Chen <yulunchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/intel/alderlake: Explicitly disable Energy Efficiency TurboJeremy Compostella2022-09-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | FSP silicon 3347 changed the default value of the EnergyEfficientTurbo Updateable Product Data (UPD), enabling the Energy Efficient Turbo feature by default. This feature prevents the cores from entering Turbo frequency under heavy load. As a result of this FSP change, coreboot explicitly disables this feature to stay consistent with commit `caa5f59279e Revert "soc/intel/alderlake: Enable energy efficiency turbo mode"'. BRANCH=firmware-brya-14505.B BUG=b:246831841 TEST=verify that bit 19 of MSR 0x1fc is set. 'iotools rdmsr 0 0x1fc' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7498f87eb4be666b34cfccd0449a2b67a92eb9db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/intel/adlrvp: enable ECT for LP5 memoryZhixing Ma2022-09-201-1/+1
| | | | | | | | | | | | | | On ADLRVP with LP5 memory, MRC team recommends enabling ECT(Early Command Training) to avoid hang during boot process. BRANCH=firmware-brya-14505.B TEST=Booted to OS on ADLRVP with LP5 memory. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I2472707825bbbdd8e5c12a714e0d40ea0b458838 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/variants/skolas: Set power limit valuesSumeet Pawnikar2022-09-202-12/+8
| | | | | | | | | | | | | | | | | Skolas board is based on Raptor Lake SoC, not Alder Lake. The code change sets CPU power limit values as performance configuration based on various Raptor Lake SoC SKUs as per the document #686872. BUG=b:242869605 BRANCH=None TEST=Built and tested on skolas board Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* qualcomm/sc7280: initialize tu struct with zerosVinod Polimera2022-09-201-3/+1
| | | | | | | | | | | | | | | Coverity is throwing a bunch of "maybe uninitialized" errors for tu struct. Initialize the tu struct with zero. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: Ie249ad4f53abc91376445420712364a28618a15a Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* mb/google/brask/variants/moli: enable ddc on DDI_PORT_2Raihow Shi2022-09-201-1/+1
| | | | | | | | | | | | | Enable ddc on DDI_PORT_2 for support DP++. BUG=b:240382609 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I475e3c0278cfa92ab40ad84f6da580b4cded9933 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Add power state thresholdsGaggery Tsai2022-09-202-0/+12
| | | | | | | | | | | | | | | | | This patch adds power state 1/2/3 threshold setting interfaces and pass the settings to FSP. BUG=b:229803757 BRANCH=None TEST=Add psi1threshold and psi2threshold to overridetree.cb and enable FSP log to ensure the settings are incorrect. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I0330ede4394ebc2d3d32e4b78297c3cb328660d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/dedede/var/boten: Turn off camera during S0ixKarthikeyan Ramasubramanian2022-09-201-0/+9
| | | | | | | | | | | | | | | | | | Add a variant specific S0ix hook to fill the SSDT table to disable and enable camera during suspend and resume respectively. BUG=b:206911455 TEST=Build Boten BIOS image. Ensure that camera is disabled during suspend and enabled during resume. Change-Id: I3229b22b8d8651bf2d9df25b10ce6749efde7cf6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
* mb/google/rex: Add WWAN ACPI supportIvy Jian2022-09-202-0/+18
| | | | | | | | | | | | | | | | | | | Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. BUG=b:244077118 TEST=check cbmem -c \_SB.PCI0.RP06: Enable RTD3 for PCI: 00:1c.5 (Intel PCIe Runtime D3) \_SB.PCI0.RP06: Enable WWAN for PCI: 00:1c.5 (Fibocom FM-350-GL) check PXSX Device is generated in ssdt. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I6114c589769d2eca882cf1a5255cf4c5937121a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/nissa/var/xivu: Add supported new memory partIan Feng2022-09-203-2/+5
| | | | | | | | | | | | | | | | | | Add new ram_id:3 (0011) for memory part K3LKCKC0BM-MGCP. DRAM Part Name ID to assign K3LKCKC0BM-MGCP 3 (0011) BUG=b:247039096 TEST=Use part_id_gen to generate related settings and emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I78d2e501b9d8d801a3d149002f638125bf4275f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* cpu/intel/haswell: Update Broadwell ULT µcode updatesAngel Pons2022-09-201-1/+1
| | | | | | | | | | | | | | | | | | The µcode updates for Broadwell come from coreboot's blobs submodule and have not been updated in at least 7 years. Use the µcode updates available in the intel-microcode submodule. This change forgoes some µcode updates for old Broadwell ULT/ULX steppings with CPUID 0x306d2 and 0x306d3, as well as an old µcode update for Haswell ULT/ULX CPUs with CPUID 0x40651 in favor of a newer intel-microcode revision that was already being used: when the µcode updates are concatenated into one file, the newer µcode update revision would be placed before the older revision, so the latter would never be used. Change-Id: I67f8a58552bd211095c183e6f7a219d60e3be162 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-12 16:17:53 +0000