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* mb/google/eve: Implement EC device events for S3 wakeDuncan Laurie2017-07-013-0/+12
| | | | | | | | | | | | | | | | | | | Add support for waking from and logging device events that originate in the Embedded Controller. As this device uses Deep S3 it relies on the EC to wake the AP from the trackpad and DSP wake sources. BUG=b:30624430 TEST=manual testing on Eve: wake from Deep S3 via trackpad and DSP and verify the event log contains the expected device event. Change-Id: I0d6a9c5bfd4cea85e13446ffaa6fe3dab0db96a2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: Add support for EC device eventsDuncan Laurie2017-07-014-1/+113
| | | | | | | | | | | | | | | | | | | | | | | Add support for the new EC device event interface which is used to report events from devices that are connected behind the EC. This can be used to differentiate wake sources from the EC in the case that the EC has the wake pins from various devices. This can be used in case the AP is unable to directly wake from the device itself, for example when using the Deep S3 state on Intel platforms only a few pins can directly wake the AP. BUG=b:30624430 TEST=build google/* boards that use chrome EC. Feature is used and tested further in a subsequent commit. Change-Id: I5126c6d6ffb6b0ef6e8db8dcd5aec62db925a371 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* elog: Update for EC Device EventsDuncan Laurie2017-07-011-1/+7
| | | | | | | | | | | | | | | | | Replace the unused "thermal overload" event with the new "device event" and define the first few device events that are supported by the Chromium EC. BUG=b:30624430 TEST=build for google/* mainboards Change-Id: I1f3aeedb87c2aad29a0a67b5c50c29a6961fb45f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: Sync header with Chromium EC codebaseDuncan Laurie2017-07-011-566/+1218
| | | | | | | | | | | | | | | | | | Update this header from the upstream source so new host commands can be used in coreboot. https://chromium.googlesource.com/chromiumos/platform/ec commit bbb759ceaa843f548f90c35d1668e17c8879bad3 BUG=b:30624430 TEST=build google/* and intel* boards Change-Id: I56c9f891262d8984b6a9a69d96752c2dd6bb2371 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mainboards: Remove unused EC event for thermal overloadDuncan Laurie2017-07-0116-16/+0
| | | | | | | | | | | | | | | | | | The Chrome EC event for "thermal overload" was never implemented and is being repurposed as the EC event mask is out of free bits. Remove this from the boards that were enabling it. BUG=b:36024430 TEST=build coreboot for affected boards Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* riscv: Update the gcc built-in macro __riscv__wxjstz2017-07-011-1/+1
| | | | | | | | | | | | | | The architecture is determined by __riscv__ in the LZ4_copy8 function (located in src / commonlib / lz4_wrapper.c). __riscv exists in gcc7.1.1. But __riscv__ does not exist. Change-Id: I38fd41da9afd76c254f0c3d6984579c3790e5792 Signed-off-by: XiangWang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/20125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Waterman <aswaterman@gmail.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
* nb/intel/i945/gma.c: Remove redefined "DISPPLANE_BGRX888"Elyes HAOUAS2017-07-011-1/+1
| | | | | | | | | | | DISPPLANE_BGRX888 defined in drivers/intel/gma/i915_reg.h included in i915.h file Change-Id: I4e9414f39a29e4eac7e325672ce6520a5654d3bc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/i945/gma.c: Add whitespace around '<<'Elyes HAOUAS2017-07-011-1/+1
| | | | | | | | | | Change-Id: Ic01bbae9acaabaade777db52825aa80d25fc5961 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_apl1: Set up RTC backup mode to primary cellWerner Zeh2017-06-301-1/+4
| | | | | | | | | | | Set RX6110SA RTC backup mode to primary cell. This mode reduces the backup current consumption of the RTC. Change-Id: I7c0c26a0ed5d8f48587acc917f8bb1c5c2b8869a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/siemens/mc_bdx1: Set up RTC backup mode to primary cellWerner Zeh2017-06-301-1/+4
| | | | | | | | | | | | | | The used RTC6110SA has issues to enter backup mode when the power supply decreases too slow when the mainboard is turned off. Switch to backup mode "primary cell" to make sure backup mode will be entered correctly on power-off. In addition set IOCUTEN to minimize the backup current consumption of the RTC. Change-Id: I9733aa9f2981a25f6d42279eff0c4980e5eb5a5a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* rx6110sa: Add a software reset sequence in case of power lossWerner Zeh2017-06-302-36/+61
| | | | | | | | | | | | | | | | | | According to the datasheet the RTC needs a power rising slope of no more than 100µs/V to ensure a correct power-on reset. If the mainboard that hosts the RTC cannot guarantee this, a software reset sequence is needed in the case where the battery was drained completely. As the rising slope of the power supply depends on so many parameters and is highly mainboard specific, refactor the initialization code to perform a software reset every time a power loss event is recognized by the RTC. Change-Id: If64d672e51667523058041bd00e1e50ac047143d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* southbridge/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-3031-59/+61
| | | | | | | | Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* lib/spd_bin: Use proper I2C addressesNico Huber2017-06-295-6/+4
| | | | | | | | | | | | | Use the plain address instead of the weird shifted encoding (e.g. if we'd use `0xa0` as address, it's actually `0x50` encoded into a write command). Change-Id: I6febb2e04e1c6de4294dfa37bde16b147a80b7a8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/skylake/Kconfig: Drop useless FSP1.1/2.0 promptsNico Huber2017-06-291-4/+2
| | | | | | | | | | | | | There is no choice, if not leaving it with the default the build will fail. Change-Id: Id91e3ce87f8ced3001fcd2125f8f6781b270f5bc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: Add UART initializationAndrey Petrov2017-06-291-0/+67
| | | | | | | | | | | Cannonlake has built-in UART driver as part of LPSS block. However port mapped decoders are in use as well. Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* arch/x86: update assembly to ensure 16-byte alignment into CAaron Durbin2017-06-292-1/+20
| | | | | | | | | | | | When the C compiler expects 16-byte alignment of the stack it is at the call instruction. Correct existing call points from assembly to ensure the stacks are aligned to 16 bytes at the call instruction. Change-Id: Icadd7a1f9284e92aecd99c30cb2acb307823682c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/common/block/gpio: Port gpio code from Apollolake to commonHannah Williams2017-06-295-0/+978
| | | | | | | | Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: Add initial dummy directoryLijian Zhao2017-06-293-0/+96
| | | | | | | | | | | | | | | Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/amd/stoneyridge: Convert monotonic timerMarshall Dawson2017-06-293-2/+56
| | | | | | | | | | | | | | | Use the TSC for the Stoney Ridge monotonic timer. Modern AMD CPUs have invariant timestamp counters. This patch brings the feature more in line with other devices and allows the use of typical monotonic timer functions. BUG=chrome-os-partner:62578062 Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/siemens/mc_bdx1: Set bus master bit for on-board PCI devicesWerner Zeh2017-06-291-0/+15
| | | | | | | | | | | | | | | | | There are up to two on-board PCI devices where bus master has to be enabled in PCI config space. As there is no need for a complete PCI driver for these devices just set the bus master bit in mainboard_final(). In a perfect world that would be the task of the runtime driver which unfortunately don't do that. Change-Id: Ic2896d5e7568a455737af26b14b2c398caae5f72 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* nb/haswell: set ASLB gnvs to OpRegion ACPI memory addressMatt DeVillier2017-06-291-0/+12
| | | | | | | | | | | | | | The ALSB gnvs variable is used to load the OpRegion memory address into the ASLS register on the S3 resume path, and must therefore first be set on the normal boot path. This patch brings Haswell in line with SNB/IVB/Nehalem, which already save the OpRegion address in ASLB. Change-Id: Ie062cbfe7e7f60c2a4e2b9111f6b6da87ced7a39 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/amd/stoneyridge: Revise pci_devs.h fileMarshall Dawson2017-06-281-59/+231
| | | | | | | | | | | | | | | | | Now that pci_devs.h is part of soc/ and not used for multiple southbridges: * Remove devices not present in the Stoney Ridge APU * Complete the list to include additional devices besides those in the FCH. BUG=chrome-os-partner:62578372 Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20370 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* soc/amd/stoneyridge: Fix device IDsMarshall Dawson2017-06-281-11/+11
| | | | | | | | | | | | | Update pci_devs.h to the correct IDs for Stoney Ridge. BUG=chrome-os-partner:62578372 Change-Id: Ic1a7fe8d95c34b80e21cc089168732372d9690a3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20200 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* amd/family15h: Add defines for boost and P-stateMarshall Dawson2017-06-281-0/+4
| | | | | | | | | | | | | | Add definitions for the P-state 0 MSR and Core Performance Boost Control. BUG=chrome-os-partner:62578062 Change-Id: I0c16dde17f1be41a3310c3ccefe3936aba0e8ec0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/amd/stoneyridge: Enable early cbmemMarshall Dawson2017-06-282-1/+12
| | | | | | | | | | | | Add a memmap file with a cbmem_top() function. Remove the LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls to the late-only set_top_of_ram() function. Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* amd/gardenia: Init cbmem in romstageMarshall Dawson2017-06-281-0/+5
| | | | | | | | Change-Id: I6ede71ec660678bb5f77693a9095aa0f198e4e26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* src/ec: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-284-7/+7
| | | | | | | | | | Change-Id: Ic2cdfa08cdae9f698eb2f8fa4c4ae061f1a7d903 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* src/device: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-286-23/+23
| | | | | | | | | | | | Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* device/oprom/yabel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-288-50/+50
| | | | | | | | | | | Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I82bf68a7ee54ff88f65aacc9eb0dbc30d013aae0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* cpu/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-289-12/+13
| | | | | | | | | | | Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* cpu/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-2820-84/+85
| | | | | | | | | | | Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I9f4155285529ec28e826637a61436478f648704c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* mainboard/google/fizz: Add audio devicesKevin Cheng2017-06-284-2/+45
| | | | | | | | | | | | | | | | - Describe RT5663 headphone codec in ACPI so it can be enumerated by the OS. - Supply NHLT binaries for RT5663 BUG=b:62872377 TEST=Apply full patch set and UCM, verify basic audio works. Signed-off-by: Kevin Cheng <kevin.cheng@intel.com> Change-Id: I5bbd58b0e660cdf5089e6a6dd35a757ecf8ec076 Reviewed-on: https://review.coreboot.org/20305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* nb/amdk8/debug.c Fix building with CONFIG_DEBUG_SMBUSArthur Heymans2017-06-282-4/+8
| | | | | | | | | | | | | Problem was introduced by fb2f667da2 "nb/amd/amdk8: Link raminit_f.c" which linked debug.c and was not tested with this option. Change-Id: I8597a6915c65ea783a864110cb23ecb34ea0611b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Swift Geek <swiftgeek@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cpu/intel/pineview: Include speedstepArthur Heymans2017-06-282-0/+2
| | | | | | | | | | Needed to generate cpu entries. Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* northbridge/amd/agesa/*: Add whitespace around '<<'Elyes HAOUAS2017-06-289-59/+59
| | | | | | | | Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cpu/*: Add whitespace around '<<'Elyes HAOUAS2017-06-2814-28/+28
| | | | | | | | Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* clang: Allow initializer overridesStefan Reinauer2017-06-272-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | In the code we do the following in a number of places to pre-initialize an array with a certain value before overwriting some of the array with other values: u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F, } clang does not like that behavior unless we specify the option -Wno-initializer-overrides. Remove the check for gcc in those places, too, because 1) it would silently change array contents between compilers 2) the check isn't sufficient to determine compilation on clang vs gcc Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I93cc121b6fec099fcdbd5fd1114c2ff7cbc291dc Reviewed-on: https://review.coreboot.org/20384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* sis/sis966: Clean up sata.cStefan Reinauer2017-06-271-114/+100
| | | | | | | | | | | | | | | | Wow, this one is disliked by clang for the empty for() loop, but looking at the file just makes my eyes bleed a little bit. I remember the circumstances under which we let this code go in. It was supposed to save contributions from a vendor, but that never worked out. Just to keep the little chunks down, here's an indent run and some of the cruft removed that doesn't actually contribute to functionality in any way. Change-Id: Ie82166ca82f09c4b66decfde5ad194a2d70b0708 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* commonlib/storage: Zero extend MMC capacityLee Leahy2017-06-271-1/+1
| | | | | | | | | | | | | | Fix CID 1376472 detected by coverity. Zero extend the capacity instead of sign extending it. TEST=Build and run on reef Change-Id: I6aac422fb1dacb75e0cc44a94ff1f467ce9f529e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* soc/amd/stoneyridge: Add tseg size to KconfigMarshall Dawson2017-06-271-0/+5
| | | | | | | | | | | | Add a SMM_TSEG_SIZE symbol that can be used in top of memory calculations. Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/stoneyridge: Remove IDE controllerMarshall Dawson2017-06-272-45/+0
| | | | | | | | | | | | | Remove IDE from the Stoney Ridge source. This APU doesn't have an IDE controller. The support was left over from pi/hudson. BUG=chrome-os-partner:62580062 Change-Id: I7316c113a7464089ccfbea6b6cf69787940b9e97 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/stoneyridge: Remove FCH PCIe supportMarshall Dawson2017-06-272-62/+0
| | | | | | | | | | | | | | | Remove the pcie.c file. Historically PCIe lanes have been available from the Gfx and/or the FCH. The integrated FCH in this APU has no PCIe available. BUG=chrome-os-partner:62580062 Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* soc/amd/stoneyridge: Remove PCIe-PCI bridgeMarshall Dawson2017-06-275-107/+21
| | | | | | | | | | | | | | | | The Stoney Ridge does not contain this bridge like some of the older Hudson FCHs. Remove this support from the source. This moves the Stoney Ridge IRQ setup to the southbridge file, hudson.c. BUG=chrome-os-partner:62580062 Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/amd/common: Fix most checkpatch errorsMarshall Dawson2017-06-2710-179/+251
| | | | | | | | | | | | | | | | | Correct the majority of reported errors and mark most of the remaining ones as todo. Some of the lines requiring a >80 break are indented too much currently. Changes to agesawrapper.c cause the build to change, so this file is also left as-is. Make hex values consistently lower-case. BUG=chrome-os-partner:622407746 Change-Id: I0464f0cafac4ee67edc95d377dcf7aab9a90c66b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/amd/stoneyridge: Fix most checkpatch errorsMarshall Dawson2017-06-2727-441/+484
| | | | | | | | | | | | | | | | | | | | | | | Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mainboard/google/soraka: Update VR config settingsRajneesh Bhardwaj2017-06-271-10/+20
| | | | | | | | | | | | | | | | | | Update Psi2Threshold, IccMax, AcLoadline, DcLoadline VR config settings as per board design. BUG=b:62063434 BRANCH=none TEST=Build and boot soraka. Change-Id: I254bbb88b82ddf278f0ec71bc98873df1d5e0d27 Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: G Naveen <naveen.g@intel.com> Reviewed-on: https://review.coreboot.org/20309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/soraka: Remove MPS IMVP8 workaroundRajneesh Bhardwaj2017-06-271-1/+0
| | | | | | | | | | | | | | | | | Soraka uses MPS2949 IMVP8 controller and does not need the VR workaroud similar to Eve. BUG=None TEST=Build & boot on soraka. Ensure IMVP8 controller goes to low power mode in S3 and S0ix by measuring power. Change-Id: Ib98bb709ecc9e362a5cef437e7319e41f398a73b Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-on: https://review.coreboot.org/20255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
* nb/intel/fsp_rangeley/port_access.c: Add brackets around macroElyes HAOUAS2017-06-271-2/+2
| | | | | | | | | | | | Code checked manually Change-Id: Idf86546ddda4fa2b4b96f0b703c03af9931c757d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* soc/amd/stoneyridge/acpi: Fix checkpatch errorsMarshall Dawson2017-06-276-54/+54
| | | | | | | | | | | | | | | | | Correct the checkpatch errors reported in the asl files and make other stylistic modifications. These changes were confirmed to cause no changes in a Gardenia build. BUG=chrome-os-partner:622407746 Change-Id: Id8b2620d161062c444e493325d83bb158705b76b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer2017-06-2753-1274/+113
| | | | | | | | | | | | | | | | | | This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 17:08:59 +0000