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* ACPI: Add top-level ASLKyösti Mälkki2021-01-27176-1/+179
| | | | | | | | | | | | | | | | | | | Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/common: Only set write_acpi_tables if ACPI table is enabledZheng Bao2021-01-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | In ./include/device/device.h, the struct device_operations is defined as below. ------------------------------------ #if CONFIG(HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(const struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt)(const struct device *dev); void (*acpi_inject_dsdt)(const struct device *dev); const char *(*acpi_name)(const struct device *dev); /* Returns the optional _HID (Hardware ID) */ const char *(*acpi_hid)(const struct device *dev); #endif ------------------------------------ So we also need to add the same #if in the C source. Change-Id: I488eceacb260ebe091495cdc3448c931cc4a1ae3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* sb,soc/amd: Rename PMOD to PICM in ASLKyösti Mälkki2021-01-2744-101/+101
| | | | | | | | | | | Use the same variable name as soc/intel to implement a common _PIC method at top-level ASL. Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/dedede/var/sasukette: Generate SPD ID for supported memory partschenzanxi2021-01-273-8/+4
| | | | | | | | | | | | | | | | Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: K4U6E3S4AA-MGCR BUG=None TEST=Build the sasukette board. Change-Id: I57c9d22ae655032120f19add98ef454853428af5 Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* ACPI: Separate device_nvs_tKyösti Mälkki2021-01-2736-289/+275
| | | | | | | | | | | | Remove typedef device_nvs_t and move struct device_nvs outside of global_nvs. Also remove padding and the reserve for chromeos_acpi_t. Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/device: Don't die() on vBIOS errorsMartin Roth2021-01-271-17/+39
| | | | | | | | | | | | | | | | | | | Systems can boot to the OS without a display. Don't kill the boot process based on a vBIOS error, instead just display a warning. If the issue is actually fatal for some reason, it's going to die at some point anyway. BUG=b:175843172 TEST=Boot morphius to OS without a display BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7d261321cdbe423dd754f6a354e5f50b53563fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/49764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/amd/common: Notify SMU of AC/DC state upon resumeMarshall Dawson2021-01-271-0/+2
| | | | | | | | | | | | | | | As a result of S3 resume, call ALIB function 1 to report the current AC/DC state. BUG=177377069 TEST=Verify printf is called during resume on Morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I3e52b0625c1222f10ea27568d5431328131a26a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/clevo: Drop redundant `select HAVE_SMI_HANDLER`Angel Pons2021-01-272-2/+0
| | | | | | | | | | Already selected from SoC Kconfig. Change-Id: I131f435ab0a30e33a70773a99c60284f8b9c82c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/amd/common/block/smbus: remove stale commentFelix Held2021-01-271-5/+0
| | | | | | | | | | | The comment doesn't apply to Stoneyridge, Picasso and Cezanne which are the only SoCs selecting SOC_AMD_COMMON_BLOCK_SMBUS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9024de9d3731a0bc64365f959142bf657a53e193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/kontron/ktqm77: Convert to ASL 2.0 syntaxElyes HAOUAS2021-01-262-3/+3
| | | | | | | | Change-Id: I7ba4625075fd3c27092d854903baf140521c8f7b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/asus/a88xm-e: Convert to ASL 2.0 syntaxElyes HAOUAS2021-01-261-3/+3
| | | | | | | | | | Generated 'build/dsdt.dsl' files are identical. Change-Id: I8887b869e9ed809f7861b810c2fb994fa2ee062e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/asus/f2a85-m: Convert to ASL 2.0 syntaxElyes HAOUAS2021-01-261-7/+7
| | | | | | | | | | Generated 'build/dsdt.dsl' are identical. Change-Id: I3a5ef0987f2e03e07f1de2b3b10d65dde3827c70 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/asus/am1i-a: Convert to ASL 2.0 syntaxElyes HAOUAS2021-01-262-16/+16
| | | | | | | | | | Generated 'build/dsdt.dsl' are identical. Change-Id: I856494c634c8c932faa7840b0fd0a35663f4de57 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46157 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/bap/ode_e20XX: Convert to ASL 2.0 syntaxElyes HAOUAS2021-01-261-4/+4
| | | | | | | | Change-Id: I07705aed2f41cd0d2a7f4b980046995f44395f07 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/asus/p2b: Convert to ASL 2.0 syntaxElyes HAOUAS2021-01-261-14/+14
| | | | | | | | | | Generated 'build/dsdt.dsl' files are identical. Change-Id: Ib07e4147f7f1b90f721be147d48ed12ae793c4fd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46159 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/t60: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS2021-01-263-5/+5
| | | | | | | | | | Generated 'build/dsdt.dsl' files are identical. Change-Id: Iea2c0600d696f9da6774affdc33d9c50d5cf2c95 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/kontron/986lcd-m: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS2021-01-261-2/+2
| | | | | | | | Change-Id: I2ef51c0348e76cb34e118ed207de88cc753f8fe0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/gigabyte/ga-945gcm-s2l: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS2021-01-261-2/+2
| | | | | | | | | | Generated 'Build/dsdt.dsl' are identical. Change-Id: Ic01ca9b58fe948fe5ffbc9e80ea4bae91fb6d581 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/msi/ms7721: Convert to ASL 2.0 syntaxElyes HAOUAS2021-01-261-7/+7
| | | | | | | | | | Generated build/dsdt.dsl files are same. Change-Id: Iaf26af76935dc8cd9642f047e833f0e8b14e6931 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46209 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/roda/rk9: Convert to ASL 2.0 syntaxElyes HAOUAS2021-01-265-146/+146
| | | | | | | | | | Generated build/dsdt.dsl are identical. Change-Id: I3cfa9d3a199a33ac8faddf4dbc1eed0df8703835 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/roda/rv11: Convert to ASL 2.0 syntaxElyes HAOUAS2021-01-262-23/+23
| | | | | | | | | | Generated build/dsdt.dsl files are identical. Change-Id: Id12c20dbe949c4badfe07578c6d202cd4cfb8191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46211 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/stout: Convert to ASL 2.0 syntaxElyes HAOUAS2021-01-263-16/+16
| | | | | | | | | | Generated 'build/dsdt.dsl' files are identical. Change-Id: I1ceb2abdd2562c145b01db7307d817c858d6b978 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/intel/braswell/romstage/romstage.c: Use __func__Elyes HAOUAS2021-01-261-3/+2
| | | | | | | | Change-Id: I07d36fb9b499e64eaba8829073c040792a2fee6e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* device/pci_device.c: Use __func__Elyes HAOUAS2021-01-261-5/+4
| | | | | | | | Change-Id: Ia6c7de99164682dcbcc375969403d2bfb9675f3c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* arch/x86/car.ld: Fix up blob reserved regionsAngel Pons2021-01-261-2/+0
| | | | | | | | | | | | | | | | | | Drop duplicated assignment that rewound `.` back, and broke platforms using MRC.bin and DCACHE_RAM_MRC_VAR_SIZE. Tested on out-of-tree Acer E5-573 (Broadwell), fixes booting. Also tested on Asrock B85M Pro4 (Haswell), also fixes booting. Change-Id: I3f0153f776c07acf7cf92808b677b118c60507c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49909 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/common/fsb.c: Add Broadwell CPUID modelsAngel Pons2021-01-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for both the traditional and ULT variants of Broadwell, because the CPU driver for Haswell already contains CPUIDs for both Broadwell types. Without this patch, Broadwell CPUs would hang when trying to print the first console log message, but only if flashconsole was not enabled. This was missed in commit f542b7bcef (cpu/intel/haswell: Add Broadwell CPUIDs and microcode) and went unnoticed until now because the tests were done with flashconsole enabled, which somehow boots properly even though the console time tracking would not work (depends on TSC). Tested on out-of-tree Acer E5-573, fixes booting without flashconsole. Change-Id: I78a1696771d4d6d2138ec432dc0d8e030f14293b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49939 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd: Add an option to select if SOC supports ESPI sub decodeZheng Bao2021-01-263-1/+8
| | | | | | | | | | | Cezanne doesn't have eSPIx00034 register define in PPR. Currently only Picasso need this option. Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/brya: Add memory DQ mapEric Lai2021-01-264-1/+108
| | | | | | | | | | | | | Add memory DQ map based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48446 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork/Kconfig.name: remove double space in board variant namesFelix Held2021-01-261-4/+4
| | | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If0bc153cd3a3391b1607848436f0ab5fcd54ce7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/ocp/deltalake: Replace space with underscore in Locator stringJohnny Lin2021-01-261-1/+1
| | | | | | | | | | | | | | Per Facebook BIOS requirements 'Locator' field should not have any space between words. Tested=On OCP Delta Lake, dmidecode -t 17 to verify. Change-Id: I2f6f1b2590c55d6da4ca32aef2f50eb332f441dc Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/volteer/var/voema: Add camera ACPI configurationDavid Wu2021-01-261-1/+272
| | | | | | | | | | | | | | | Add camera ACPI configuration for Voema BUG=b:169551066 TEST=Build and boot Voema. Start camera app and able to capture images. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I903e5e0b5f85718c7c9cbb6d5cafb8fc9ad5814e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jim Lai <jim.lai@intel.com>
* ocp/deltalake: Set C-State configMarc Jones2021-01-261-0/+2
| | | | | | | | | | | | Set the supported C-State to C1 and C6. This matches the states in CPUID(5). Change-Id: If32b8256097b5b2bee7fb074fab105e4b54d14b3 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49803 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp/acpi.c: Add ACPI C-State tableMarc Jones2021-01-265-2/+103
| | | | | | | | | | | | | | | | Add the soc ACPI _CST table. The table may be customized to support the different state combinations and set by the mainboard config. Tested on deltalake with acpi_idle driver. Note, intel_idle may not use ACPI _CST table. Change-Id: I359daa9556edbe263ab0a7f1849c96c8fe1a0da0 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
* soc/intel: Move c-state resource defineMarc Jones2021-01-268-63/+10
| | | | | | | | | | | De-duplicate the MWAIT_RES define. Move it to intel/common/block. Change-Id: I43903e4f02a549f53101e79f6febd42f2e54f98f Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49802 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb,soc/intel: Refactor power_on_after_fail optionKyösti Mälkki2021-01-263-41/+46
| | | | | | | | | | It's only necessary to call get_option() with SLP_TYP S5. Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49251 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/smm: Remove unused APMC for C-state and P-stateKyösti Mälkki2021-01-262-8/+0
| | | | | | | | Change-Id: I7a3a1b63c0ef14b1e24ecce2df66f7970e5eb669 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd: Refactor some ACPI S3 callsKyösti Mälkki2021-01-268-31/+14
| | | | | | | | | | | | | | | | | | | | Do not pass ACPI S3 state as a parameter, by locally calling acpi_is_wakeup_s3() compiler has better chance for optimizing HAVE_ACPI_RESUME=n case. Test for acpi_s3_allowed() is already included in the implementation of acpi_is_wakeup_s3() and is removed as redunandant. For ramstage, acpi_is_wakeup_s3() evaluates to romstage_handoff_if_resume(). Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/auron: Use `get_gpios` functionAngel Pons2021-01-256-79/+22
| | | | | | | | Change-Id: I91424a45ae67186987630b7686102f467f57e7ee Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/amd/picasso: Change GPIO _HID to AMDI0030Raul E Rangel2021-01-251-1/+1
| | | | | | | | | | | | | | This matches the _HID used in the picasso UEFI bios. BUG=none BRANCH=zork TEST=boot linux and verify peripherals still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ieb441696cbe67a772632990347c12d1d15cfaf13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/picasso/acpi: Change I2C _HID to AMDI0010Raul E Rangel2021-01-251-2/+2
| | | | | | | | | | | | | | | | | This is the new _HID that was used for Raven. It matches the _HID used by the picasso UEFI bios. This does change the fixed clock used by linux from 133 MHz to 150 MHz. BUG=none BRANCH=zork TEST=boot linux and verify touch screen and touchpad still function Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I37fcb4a4f0148f4843d026902d694c03aeed3c3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/picasso/acpi: Change UART _HID to AMDI0020Raul E Rangel2021-01-251-4/+4
| | | | | | | | | | | | | | | This is the new _HID that was used for Raven. It matches the _HID used by the picasso UEFI bios. BUG=none BRANCH=zork TEST=boot linux and verify UART still works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I138cb445c84997f4a4006cbb4f6617dac25a61b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/denverton_ns: Drop unused `pattrs.h`Angel Pons2021-01-251-40/+0
| | | | | | | | | | Change-Id: I78ff11a56b38c4bc4f4f00115de1af4b73d4448c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driverFurquan Shaikh2021-01-255-289/+428
| | | | | | | | | | | | | | | | This change uses the newly added meminit block driver and updates ADL SoC and mainboard code accordingly. BUG=b:172978729 Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* soc/amd/picasso: Use makefile variable to locate UCODEZheng Bao2021-01-251-1/+1
| | | | | | | | | | | Change the hardcoded location of microcode patches to using FIRMWARE_LOCATION. Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49734 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common: Refactor ACPI wake sourceKyösti Mälkki2021-01-251-10/+9
| | | | | | | | | Change-Id: I5cb65e131bf2a35c4305ea971812d9799b964c4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49837 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd: Refactor ACPI power state and ELOGKyösti Mälkki2021-01-258-23/+30
| | | | | | | | Change-Id: Ib7423c8d80355871393c377ebaffdfe2846d8852 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb,soc/intel: Remove no-op APMC for C-state and P-stateKyösti Mälkki2021-01-2511-100/+0
| | | | | | | | Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49250 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/common: Change some SMI loggingKyösti Mälkki2021-01-254-20/+2
| | | | | | | | Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49249 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/smm: Use common APMC loggingKyösti Mälkki2021-01-2515-77/+35
| | | | | | | | | | Unify the debug messages on raised SMIs. Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/drawcia: Add support to handle pen detectionWisley Chen2021-01-253-0/+48
| | | | | | | | | | | | | | | | For board version 6 afterward, it will have external pull-up for GPP_C12, and remove internal pull-up. BUG=b:177618684 TEST=emerge-dedede coreboot, check evtest if SW_PEN_INSERTED event (value:1/0) when insert/eject pen, and eject pen to wake system from s0ix Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I503873afb48384168dcd8a822c7246655898356e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-27 18:43:48 +0000