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* mb/google/eve: Enable VMXDuncan Laurie2017-11-141-0/+1
* mb/google/eve: Tune I2C4 hold timesDuncan Laurie2017-11-141-2/+6
* mb/google/eve: Enable AER and LTRFurquan Shaikh2017-11-141-0/+4
* mb/google/eve: Use rt5663 driver and set propertiesDuncan Laurie2017-11-142-4/+6
* mb/google/eve: Remove ACPI control of touchscreen powerDuncan Laurie2017-11-143-7/+8
* mb/amd/gardenia: Remove direct AGESA header includesMartin Roth2017-11-144-8/+2
* soc/amd/stoneyridge: Remove direct AGESA header includesMartin Roth2017-11-146-23/+5
* soc/amd/common: Remove direct AGESA header includesMartin Roth2017-11-146-16/+6
* mb/google/kahlee: Remove direct AGESA header includesMartin Roth2017-11-145-9/+4
* AMD Stoney Ridge: Add agesa_headers.hMartin Roth2017-11-142-2/+34
* ec/lenovo/h8/acpi/ec: Add registersPatrick Rudolph2017-11-141-0/+24
* amd/common/spi: Update flash driver usageMarshall Dawson2017-11-141-8/+8
* soc/amd/stoneyridge: Load SMU fimware using PSPMarshall Dawson2017-11-143-2/+41
* amd/stoneyridge: Add generic IMC sleep and wakeupMarshall Dawson2017-11-142-0/+12
* amd/stoneyridge: Replace BIT(n) in southbridgeMarshall Dawson2017-11-141-4/+5
* amd/stoneyridge: Define bits for AcpiConfigMarshall Dawson2017-11-141-0/+13
* mb/google/kahlee: Add getter function for GPIO arrayMartin Roth2017-11-134-6/+17
* mb/google/kahlee: Remove mainboard.hMartin Roth2017-11-135-26/+5
* mainboard/google/kahlee: Add Grunt variant frameworkMartin Roth2017-11-135-5/+92
* mainboard/google/kahlee: Add baseboard frameworkMartin Roth2017-11-134-0/+121
* soc/intel/common: Add error print in common i2cLijian Zhao2017-11-131-3/+2
* soc/intel/cannonlake: Define default LPSS clockLijian Zhao2017-11-131-0/+4
* soc/amd/stoneyridge: Add CPU PPKG ASLMarc Jones2017-11-131-0/+17
* soc/amd/stoneyridge: Add GNVS variables for thermal controlMarc Jones2017-11-132-1/+13
* amd/gardenia: Add globalnvs.aslMarc Jones2017-11-131-0/+3
* soc/amd/stoneyridge: Fix DRAM clear checkMarshall Dawson2017-11-131-1/+3
* google/chell: add missing SPD hex filesMatt DeVillier2017-11-137-4/+89
* intel/fsp: Update cannonlake FSP headerLijian Zhao2017-11-113-15/+38
* vendorcode/amd/pi/00670f00: Set ModuleIdentifier to be 8 bytesMartin Roth2017-11-111-1/+1
* soc/intel/apollolake: Make use of Intel SPI common blockSubrata Banik2017-11-113-11/+3
* soc/intel/apollolake: Add support for SPI deviceSubrata Banik2017-11-111-0/+28
* soc/intel/cannonlake: Make use of Intel SPI common blockSubrata Banik2017-11-113-56/+2
* soc/intel/skylake: Make use of Intel SPI common blockSubrata Banik2017-11-113-52/+3
* soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routineSubrata Banik2017-11-116-46/+64
* soc/intel/common/block: Add Intel common SPI supportSubrata Banik2017-11-114-0/+130
* google/kahlee: Use devicetree register values for UMAMarshall Dawson2017-11-101-0/+2
* soc/amd/stoneyridge: Add UMA settings to devicetreeAaron Durbin2017-11-102-0/+39
* amd/stoneyridge: Implement vboot_platform_is_resumingMarshall Dawson2017-11-102-0/+12
* amd/stoneyridge: Add function to find Pm1EvtBlk baseMarshall Dawson2017-11-102-0/+6
* amd/stoneyridge: Remove dead southbridge definitionsMarshall Dawson2017-11-101-9/+0
* amd/stoneyridge: Add more ACPI register definitionsMarshall Dawson2017-11-101-0/+12
* amd/stoneyridge: Use the new generic acpi_sleep_from_pm1Marshall Dawson2017-11-101-3/+1
* amd/stoneyridge: Select AMD common sleep statesMarshall Dawson2017-11-101-0/+1
* arch/x86: Add common AMD ACPI hardware definitionsMarshall Dawson2017-11-102-12/+28
* soc/amd/stoneyridge: Use uint8_t as type for SPD addressRichard Spiegel2017-11-103-5/+5
* soc/amd/stoneyridge: Simplify and fix SMBUS codeRichard Spiegel2017-11-105-133/+74
* google/kahlee: Add defines in OemCustomize.cMarshall Dawson2017-11-101-2/+8
* google/kahlee: Move DRAM clear override to devicetreeMarshall Dawson2017-11-102-2/+1
* soc/amd/common: Add DRAM clear option to northbridge.cRichard Spiegel2017-11-104-4/+28
* soc/intel/cannonlake: Remove structure variable initialization with 0Subrata Banik2017-11-101-3/+0
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