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* baytrail mainboards: Clean up mainboard.cArthur Heymans2020-08-052-29/+2
* include/device/azalia_device.h: Include <stdint.h>Elyes HAOUAS2020-08-051-1/+1
* mb/google/zork: update DRAM SPD table for dirinbozKevin Chiu2020-08-051-0/+25
* soc/intel/common: Include Alder Lake device IDsSubrata Banik2020-08-0519-2/+447
* nb/intel/x4x: Define and use `HOST_BRIDGE` macroAngel Pons2020-08-046-52/+52
* Revert "device/pci_device.c: Do not complain about disabled devices"Nico Huber2020-08-041-4/+0
* soc/intel/skylake: Add RMRRs after all DRHDsAngel Pons2020-08-041-11/+18
* soc/intel/broadwell: Add RMRRs after all DRHDsAngel Pons2020-08-041-11/+18
* soc/intel/apollolake/acpi.c: Add RMRRs after all DRHDsAngel Pons2020-08-041-8/+13
* nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDsAngel Pons2020-08-041-16/+22
* nb/intel/x4x: Remove dead assignmentsAngel Pons2020-08-041-2/+1
* soc/amd/picasso/acpi: clean up global NVSFelix Held2020-08-042-40/+20
* nb/intel/x4x: Refactor `decode_pcie_bar`Angel Pons2020-08-041-9/+5
* nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decodingAngel Pons2020-08-041-28/+28
* nb/intel/i945: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-32/+7
* nb/intel/i945: Refactor `get_pcie_bar`Angel Pons2020-08-041-19/+20
* nb/intel/haswell: Use ASL 2.0 syntaxAngel Pons2020-08-041-3/+3
* sb/intel/i82801gx: Use PCI bitwise opsAngel Pons2020-08-048-127/+45
* nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntaxAngel Pons2020-08-041-34/+32
* nb/intel/sandybridge: Update to ASL 2.0 syntaxAngel Pons2020-08-041-4/+4
* nb/intel/x4x: Change signature of `decode_pciebar`Angel Pons2020-08-044-4/+4
* nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-35/+11
* nb/intel/pineview: Refactor `decode_pcie_bar`Angel Pons2020-08-041-9/+5
* nb/intel/pineview: Change signature of `decode_pciebar`Angel Pons2020-08-044-4/+4
* nb/intel/pineview: Use `MiB` definitionAngel Pons2020-08-043-9/+10
* mb/google/zork/var/vilboz: Enable support for garaged stylusFurquan Shaikh2020-08-041-0/+12
* mb/kontron/bsl6: Add new Skylake COMe moduleNico Huber2020-08-0421-0/+794
* soc/intel/baytrail: Factor out `acpi_fill_madt()`Angel Pons2020-08-043-35/+15
* mb/supermicro/x11ssh-tf: Drop `PcieRpClkReqSupport` linesAngel Pons2020-08-041-4/+0
* nb/intel/pineview: Remove dead assignmentsAngel Pons2020-08-041-2/+1
* nb/intel/gm45: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-32/+6
* nb/intel/gm45/northbridge.c: Use `MiB` definitionAngel Pons2020-08-041-3/+4
* nb/intel/gm45: Use PCI bitwise opsAngel Pons2020-08-048-140/+74
* mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons2020-08-0422-210/+210
* nb/intel/i440bx: Make ROM area unavailable for MMIOKeith Hui2020-08-041-0/+1
* src/lib: Remove unused function parameters in imd.cAnna Karas2020-08-044-15/+14
* mb/gizmosphere/gizmo/mainboard.c: Remove white space after 'mdelay'Elyes HAOUAS2020-08-031-1/+1
* mb/google/zork: Pass oscout system clk to rt5682Akshu Agrawal2020-08-032-2/+8
* soc/amd/picasso: set is_rv to 1 for RV familyAkshu Agrawal2020-08-031-0/+8
* mb/bostentech: Add GBYT4 portMate Kukri2020-08-0319-0/+674
* soc/intel/baytrail: Add MRC SMBus workaroundMate Kukri2020-08-031-1/+17
* lib/gcov: Remove assert(0)Patrick Georgi2020-08-031-1/+1
* soc/intel/xeon_sp/cpx: configure STACK_SIZEJonathan Zhang2020-08-031-0/+4
* soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2Jonathan Zhang2020-08-035-21/+22
* mb/asrock/h110m: Relocate devicetree settingsAngel Pons2020-08-031-114/+97
* nb/intel/ironlake: Add Generic Non-Core register definitionsAngel Pons2020-08-033-4/+8
* nb/intel/ironlake: Add Generic Non-Core PCI device definitionAngel Pons2020-08-033-4/+9
* nb/intel/ironlake: Add QPI Physical Layer registersAngel Pons2020-08-032-13/+23
* nb/intel/ironlake: Add QPI Physical Layer device definitionAngel Pons2020-08-032-13/+18
* nb/intel/ironlake: Add QPI Link register definitionsAngel Pons2020-08-032-5/+10
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